Cadence (Ambit) synthesis pragmas

From: Paul Graham (pgraham@cadence.com)
Date: Thu Dec 06 2001 - 12:50:12 PST

• Next message: Paul Graham: "LRM error: task syntax"
• Previous message: Shalom Bresticker: "New html BNF"
• Messages sorted by: [ date ] [ thread ] [ subject ] [ author ] [ attachment ]

Precedence: bulk

Cliff,

Here's Cadence's list of synthesis pragmas. All our synthesis pragmas begin
with "ambit synthesis", so I'll leave off that prefix:

        // your favorite, Cliff
    case = full,mux,parallel

        // specify an architecture: cla, ripple, etc.
    architecture = "cla"

        // sets boundary on operator merging
    merge_boundary

        // specify set/reset control for registers inferred from named blocks
    set_reset [a]synchronous blocks = "a,b,c"

        // specify signals to connect to [a]synchronous set/reset pins
    set_reset [a]synchronous signals = "s1,s2,s3"

        // specify signals in block "a" only to connect to [a]synchronous
        // set/reset pins
        // This one may be hard to massage into a Verilog-2001 attribute
    set_reset [a]synchronous block(a) = "s1,s2,s3"

Paul

• Next message: Paul Graham: "LRM error: task syntax"
• Previous message: Shalom Bresticker: "New html BNF"
• Messages sorted by: [ date ] [ thread ] [ subject ] [ author ] [ attachment ]

This archive was generated by hypermail 2.1.4 : Mon Jul 08 2002 - 12:54:48 PDT and
sponsored by Boyd Technology, Inc.