RE: lrm error: sign of logical op

From: J. Bhasker (jbhasker@cadence.com)
Date: Tue Dec 11 2001 - 11:19:24 PST

Precedence: bulk

Paul:

Comparison results are unsigned. Says so in section 4.5.1. Did you find a
conflicting
statement somewhere else?

- bhasker 

--

J. Bhasker
Cadence Design Systems
7535 Windsor Drive, Suite A200, Allentown, PA 18195
(610) 398-6312, (610) 530-7985(fax), jbhasker@cadence.com

<p>-----Original Message-----
From: owner-btf@boyd.com [mailto:owner-btf@boyd.com]On Behalf Of Paul
Graham
Sent: Tuesday, December 11, 2001 1:41 PM
To: btf@boyd.com
Subject: lrm error: sign of logical op

<p>Precedence: bulk

Consider this example:

    module m(q, d1, d2);
	output [7:0] q;
	input signed [7:0] d1, d2;

	assign q = d1 && d2;
    endmodule

Since operands d1 and d2 are signed, the result of (d1 && d2) should be
signed, correct?  Furthermore the result is one bit wide.  So it must be
sign extended before assignment to q.  If the result is 1'b1, then with sign
extension it will be 8'b11111111.

Yet that is not how verilog-xl does it.  verilog-xl apparently treats the
result of a logical operator as an unsigned bit.  This makes perfect sense
to me, but it appears to violate the lrm.  It seems that the result of a
logical operation should always be considered unsigned.

Any comments?

Paul

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