From: Dennis Marsa (drm@xilinx.com)
Date: Fri Dec 14 2001 - 10:54:31 PST
Precedence: bulk
Is there any requirement that compiler directives appear
alone on the source line in which they appear?
Or, is allowable to have whitespace/comments/tokens/directives
before or after a compiler directive on the same source line?
Section 19 of 1364-2001 on Compiler directives does not seem
to say anything wrt to this issue, other than in section 19.5
on `include's which says that only whitespace and comments
can follow an `include directive, but nothing is said about
what can precede an `include.
All examples in Section 19 show compiler directives alone
on their own line.
I have seen code such as:
module foo;
`ifdef ABC reg a; `else reg b; `endif
endmodule
which is accepted by Verilog-XL and MTI.
Was it the intent of the standard to permit such syntax?
If so, why is `include different?
I believe Section 19 should be enhanced to address these
issues.
<p>Dennis Marsa
Xilinx, Inc.
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