From: Paul Graham (pgraham@cadence.com)
Date: Fri Dec 14 2001 - 11:23:38 PST
Precedence: bulk
> Is there any requirement that compiler directives appear
> alone on the source line in which they appear?
>
> Or, is allowable to have whitespace/comments/tokens/directives
> before or after a compiler directive on the same source line?
Verilog compiler directives look a lot like C preprocessor directives. One
exception is that a C macro is expanded unconditionally, while a verilog
macro requires the preceding `. So verilog macro references and compiler
directives are identical in syntax. It follows that a verilog compiler
directive can occur wherever a macro reference can occur, including within
a line, etc.
Paul
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