From: Dennis Marsa (drm@xilinx.com)
Date: Fri Dec 14 2001 - 12:43:14 PST
Precedence: bulk
Paul Graham wrote:
>
> Precedence: bulk
>
> > Is there any requirement that compiler directives appear
> > alone on the source line in which they appear?
> >
> > Or, is allowable to have whitespace/comments/tokens/directives
> > before or after a compiler directive on the same source line?
>
> Verilog compiler directives look a lot like C preprocessor directives. One
> exception is that a C macro is expanded unconditionally, while a verilog
> macro requires the preceding `. So verilog macro references and compiler
> directives are identical in syntax. It follows that a verilog compiler
> directive can occur wherever a macro reference can occur, including within
> a line, etc.
Though, for some reason, `include is documented as being different. Why?
IEEE 1364-2001, Section 19.5, page 357, middle of page says:
"Only whitespace or a comment may appear on the same line as the `include
compiler directive."
<p>Dennis
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