attributes and design elaboration

From: Dennis Marsa (drm@xilinx.com)
Date: Thu Jan 17 2002 - 15:27:46 PST


Precedence: bulk

Good day,

I've been thinking about attributes and how they should
be propagated during the design elaboration process.

This is a topic that does not appear to be discussed at
all in 1364-2001.

Specifically, I am wondering how attritutes attached
to items that are syntactically distinct, but
semantically related, should be processed.

For example:

   module declarations and module instantiations
   port declarations and port connections
   parameter declarations and defparams
   parameter declarations and module instance parameter overrides

I am thinking of these issues in terms of extracting attribute
information using the VPI interface.

Specific questions appear below.

Any insights you may have would be appeciated.

Cheers,

Dennis Marsa
Xilinx, Inc.

--------------------------------------------------------------------

1. Module Declaration and Module Instantiation Attributes
---------------------------------------------------------

   According to the BNF in 1364-2001, attributes can be attached to both
   a module declaration and a module instantiation.

      module top;
        (* inst_0 *) modA A0(); // module instantiation attribute
        (* inst_1 *) modA A1(); // module instantiation attribute
        (* inst_2 *) modA A2(); // module instantiation attribute
      endmodule

      (* decl *) // module declaration attribute
      module modA;
      endmodule

   QUESTION 1: When a design is elaborated, how should the module
      declaration and module instantiation attributes be propagated
      in the elaborated design?

   When elaborated, the design would have the following structure:

                       +-----+
                       | top |
                       +-----+
                          |
               +----------+----------+
               | | |
            +-----+ +-----+ +-----+
            | A0 | | A1 | | A2 |
            +-----+ +-----+ +-----+

   How are the attributes specified in the source code attached to this
   design structure?

   QUESTION 2: What happens if the same attribute is attached to a
      module declaration and an instantiation of that module? Should
      one override the other?

2. Port Attributes
------------------

   According to the BNF in 1364-2001, attributes can be attached to
   port declarations, i.e. "input", "inout" and "output" declarations.

   "input", "inout" and "output" declarations correspond directly with
   "IODECL" objects in the VPI interface.

   QUESTION 1: The VPI object diagram for attributes in section 26.6.42
      of 1364-2001 does not show "IODECL" objects as having a one-to-many
      relationship with "ATTRIBUTE" objects. Should "IODECL" be included
      in section 26.6.2?

   QUESTION 2: The VPI object diagram for attributes does show "PORT"
      objects as having a one-to-many relationship with "ATTRIBUTE"
      objects. Should attributes attached to port declarations be
      attached to "PORT" objects?

   Consider a module containing a port defined as a concatenation:

      module concat(.a({x,y,z}));
        (* input_x *) input x;
        (* input_y *) input y;
        (* input_z *) input z;
      endmodule

   QUESTION 3: Are each of the three attributes "input_x", "input_y" and
      "input_z" attached to port "a"?

   QUESTION 4: Should the BNF allow attributes to be attached to
      port references (i.e. BNF rule "port")? This would permit:

      module concat((* port_attribute *) .a({x,y,z}));
        ...
      endmodule
      
      NOTE: The BNF of 1364-2001 does not allow this currently.

3. Port Connection Attributes
-----------------------------

   According to the BNF in 1364-2001, attributes can be attached to individual
   port connections in module/udp/primitive instantiations.

      module top;
        wire a, b;
        modA A((* connection_1 *) a, (* connection_2 *) b);
      endmodule

      module modA(x, y);
        input x;
        output y;
      endmodule
      
   QUESTION 1: How should the attributes attached to the port connections
      be propagated during design elaboration? Should they be attached to
      (and combined with the attributes of) the corresponding port of
      the instantiated module?

4. DefParam Attributes
----------------------

   According to the BNF in 1364-2001, attributes can be attached to defparam
   statements.

      module top;
        (* override *) defparam top.A.a = 123;
        modA A();
      endmodule

      module modA;
        parameter a = 1;
      endmodule
      
   QUESTION 1: Should the attribute "override" be attached to or
      combined with the attributes of the parameter "a" in instance "A"
      of module "modA"? Or should "override" only appear as an
      attribute of the defparam?

5. Parameter Assign Attributes
------------------------------

   According to the BNF in 1364-2001, attributes can be attached to parameter
   assignments in module instantiations.

      module top;
        modA #((* override *) 123) A();
      endmodule

      module modA;
        parameter a = 1;
      endmodule
      
   QUESTION 1: Should the attribute "override" be attached to or
      combined with the attributes of the parameter "a" in instance "A"
      of module "modA"? Or should "override" only appear as an
      attribute of the parameter assignment?

6. Generate Attributes
----------------------

  According to the BNF in 1364-2001, attributes can be attached to
  a "generate-endgenerate" structure, but not to generate items within
  that structure.

  QUESTION 1: What happens to the attributes attached generate/endgenerate
     structure during the design elaboration process? The
     generate/endgenerate structure will be replaced by its expansion in
     the elaborated design.



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