From: Don Mills (mills@lcdm-eng.com)
Date: Fri Feb 01 2002 - 13:17:49 PST
Precedence: bulk
Yes, the difference is when index is a variable rather then a constant. If both the vector and the index can vary, then the @(*) should be the same as always @( vector or b ) .
Michael McNamara wrote:
> I believe the question more relates to expanding:
>
> always @(*) begin
> a = vector[b];
> end
>
> One might map this to:
>
> always @( vector or b ) begin
> a = vector[b];
> end
>
> to capture vector changing when b does not change; and b changing when
> vector does not change.
>
> The reason to do this is because version of I believe Verilog-XL did
> not correctly support bitselects in sensitivity lists; so the above
> expansion is safe, but perhaps more compute intensive than necessary;
> and hence this is what my verilog mode (http://www.verilog.com/> does
> for autosensitivity.
>
> -mac
>
> Dennis Marsa writes:
> > Precedence: bulk
> >
> > Don Mills wrote:
> > >
> > > Precedence: bulk
> > >
> > > Maybe I am a little daft, but if the bit or part is a constant, how will
> > > the sensitivity list ever be triggered by it. I would think that the
> > > behavior of @(*) should follow the same behavior as before the @(*) was
> > > available. That is if I had
> > >
> > > 1) A bit-select of a vector
> > >
> > > reg [31:0] vector;
> > >
> > > always @(vector) or @(vector[5]) ??
> > > out = vector[5];
> > >
> > > The @vector[5] would be sufficient and should be legal (correct me
> > > if I am wrong here.). Having the whole vector present in the sensitivity
> > > list will also work but would slow simulation down.
> >
> > I'm not sure, but I think you may have interpreted my
> > example differently than I intended.
> >
> > I am not asking if both vector and vector[5] should be
> > in the implicit event list. It should be one or the other,
> > but which one?
> >
> > What I was asking is, should:
> >
> > always @(*)
> > out = vector[5];
> >
> > be considered equivalent to:
> >
> > always @(vector)
> > out = vector[5];
> >
> > or
> >
> > always @(vector[5])
> > out = vector[5];
> >
> > I was *not* asking if it should be interpreted as:
> >
> > always @(vector or vector[5]) // no
> > out = vector[5];
> >
> >
> > I am also interested in the case where an array
> > is substituted for the vector:
> >
> > reg [31:0] ram[0:1023];
> >
> > always @(*)
> > out = ram[5];
> >
> > Should the above be considered equivalent to:
> >
> > always @(ram)
> > out = ram[5];
> >
> > or
> >
> > always @(ram[5])
> > out = ram[5];
> >
> >
> > Regards,
> >
> > Dennis Marsa
> > Xilinx, Inc.
> >
-- ========================================================== Don Mills LCDM Engineering (Logic, Coding, & Design Methodology) mills@lcdm-eng.com www.lcdm-eng.com 801-282-6560 Office PHONE 801-641-5882 Mobile PHONE 4158 W. Ben Armine Cir., South Jordan, UT 84095-9101 ==========================================================
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