From: Dennis Marsa (drm@xilinx.com)
Date: Fri Feb 01 2002 - 13:41:03 PST
Precedence: bulk
Paul Graham wrote:
>
> Precedence: bulk
>
> > I am also interested in the case where an array
> > is substituted for the vector:
> >
> > reg [31:0] ram[0:1023];
> >
> > always @(*)
> > out = ram[5];
> >
> > Should the above be considered equivalent to:
> >
> > always @(ram)
> > out = ram[5];
> >
> > or
> >
> > always @(ram[5])
> > out = ram[5];
>
> It can't be equivalent to 'always @(ram)' because that is illegal. A
> memory must always be indexed.
Illegal in Verilog-XL? Or illegal in Verilog, period?
Correct me if I am wrong, but I don't think 1364-2001 says anything
about always @(ram) being illegal.
Dennis Marsa
Xilinx, Inc.
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