From: Michael McNamara (mac@verisity.com)
Date: Thu Feb 07 2002 - 08:33:16 PST
Precedence: bulk
Dennis Marsa writes:
> Jayaram Bhasker wrote:
> >
> > Mac:
> >
> > > > So, if any element of mem8x10 other the element 10 changes,
> > > > this statement would not be re-evaluated. Is that the
> > > > proper interpretation of @(*) in this context?
> >
> > >Yes.
> >
> > There is something not right here. Given this interpretation, there can be
> > mismatches between the implied hardware and the simulation behavior. For ex, if
> > mem8x10[7] changes, the always stmt will not execute, but the implied hardware will
> > execute and "a" will get a new value.
> >
> > My interpretation would be that since a variable index is being used on a memory(mem8x10[b]),
> > the entire memory (mem8x10) needs to be part of the event list to keep the
> > semantics of the implied hardware and simulation to match. In other words, my interpretation
> > of @* would be:
> >
> > always @(mem8x10[10] or mem8x10[0] or mem8x10[1] or mem8x10[2] or mem8x10[3] or ....<list with all
> > index values>)
>
> This is the way I would prefer to interpret it as well.
>
> One could shorten it to @(mem8x10[10] or mem8x10) if one
> defines the event mem8x10 to mean exactly as you show above:
>
> mem8x10[0] or mem8x10[1] or mem8x10[2] or ...
>
> This makes the semantics of array selects in a @(*) consistent
> with vector selects; i.e. if a variable index is used, then we
> are sensitive to the entire array (or vector).
>
> Dennis Marsa
> Xilinx, Inc.
>
OK, I now understand that the subject is code like:
reg [31:0] a,b, mem8x10[1024:0];
assign a = mem8x10[b]; // statment 1
or eqivalently
reg [31:0] a,b, mem8x10[1024:0];
always @(*) a = mem8x10[b]; // statement 2
And still I sumbit that correct behaviour can be achieved by
reg [31:0] a,b, mem8x10[1024:0];
always @(mem8x10[b]) a = mem8x10[b]; // statement 3
I question you: how does your verilog tool implement statement 1
today?
I know that VCS implements statement 1 just like statement 3.
The only reason vector selects are executed if any bit of the vector
changed was due to (IMHO) a bug in Verilog-XL version 1.6. It is
quite possible that NC verilog no longer does this; a test is in
order.
-mac
This archive was generated by hypermail 2.1.4
: Mon Jul 08 2002 - 12:55:35 PDT
and
sponsored by Boyd Technology, Inc.