From: Paul Graham (pgraham@cadence.com)
Date: Fri Mar 01 2002 - 09:50:49 PST
Precedence: bulk
> I like first part (result is real if either operand is real),
> but not the second. The second operand could be a variable,
> and at compilation time we would not necessarily know if it
> is negative or not.
>
> integer x, y;
>
> x ** y; // real or integer?
>
> Shouldn't the result type be determinable statically?
VHDL gets around the problem by defining two exponent operators:
integer ** integer => integer
real ** integer => real
The second operand may be negative only if the first operand is real. So
some run-time checking must be done. VHDL is full of run-time checking, so
this is not much of a burden.
So for verilog we could say:
The first operand to the power operator may be any integer or real type.
The second operand must be of an integer type. The result of the power
operator shall be real if and only if the first operand is real. If
the first operand is of an integer type, and the second operand is negative,
the result is undefined (or zero, or an error?).
I don't know if verilog defines the concept of an integer type, but I basically
mean any type whose value can be represented as an integer. This excludes time,
real, and realtime.
Paul
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