From: Stefen Boyd (stefen@boyd.com)
Date: Fri Mar 01 2002 - 09:58:47 PST
Precedence: bulk
At 09:50 AM 3/1/2002 -0800, you wrote:
>So for verilog we could say:
>
> The first operand to the power operator may be any integer or real type.
> The second operand must be of an integer type. The result of the power
> operator shall be real if and only if the first operand is real. If
> the first operand is of an integer type, and the second operand is
> negative,
> the result is undefined (or zero, or an error?).
>
>I don't know if verilog defines the concept of an integer type, but I
>basically
>mean any type whose value can be represented as an integer. This excludes
>time,
>real, and realtime.
Another approach would be to specify the result as an integer
only when the second operand is a non-negative constant expression.
This would be closer to the intended uses and keeps us from having
to force the first operand to be a real when we want a real result.
I believe the only places we *have* to have an integer value are
where we need constant expressions anyhow.
Regards,
Stefen
--------------------
Stefen Boyd Boyd Technology, Inc.
stefen@BoydTechInc.com (408)739-BOYD
www.BoydTechInc.com (408)739-1402 (fax)
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