From: Dennis Marsa (email@example.com)
Date: Fri Mar 01 2002 - 10:11:36 PST
Paul Graham wrote:
> VHDL gets around the problem by defining two exponent operators:
> integer ** integer => integer
> real ** integer => real
> The second operand may be negative only if the first operand is real. So
> some run-time checking must be done. VHDL is full of run-time checking, so
> this is not much of a burden.
> So for verilog we could say:
> The first operand to the power operator may be any integer or real type.
> The second operand must be of an integer type. The result of the power
> operator shall be real if and only if the first operand is real. If
> the first operand is of an integer type, and the second operand is negative,
> the result is undefined (or zero, or an error?).
I like it, but would suggest changing the second sentence to:
The result type of the power operator shall be the type of the first operand.
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