From: Shalom Bresticker (Shalom.Bresticker@motorola.com)
Date: Wed Apr 24 2002 - 23:28:34 PDT
While I also remembered that Verilog-2001 added the ability to do assignment to a bit-select or part-select of an array, I have been
unable to find an explicit reference to this neither in the LRM itself nor in my email archives.
Other relevant sections of the LRM are 3.10, 4.2, and Table 6-1.
It is unfortunate that the texts relating to a single subject are spread out over 3 or 4 different places.
It causes discrepancies. It also means that you read one section and are missing the supplemental information which appears in
another section, you don't know you're missing it, and you don't even know where to look for it.
The IEEE version doesn't even have an index or a detailed Table of Contents.
Unfortunately, there are a lot of cases like this.
Specifically with respect to this issue, it would be good to review every reference to "memory" in the LRM,
and check whether it should be "memory" or "array", and check whether it is still accurate.
What a headache !
Shalom
> >Date: Wed, 24 Apr 2002 11:56:05 -0700
> >From: Gordon Vreugdenhil <gvreugde@synopsys.com>
> >
> >I ran into an apparent grammar/interpretation issue in the Verilog
> >2001 LRM. The issue is a conflict between the grammars in Figs.
> >9-1 and 9-2 versus the text at the beginning of 9.2. The grammar
> >allows left hand side range selects on a memory/array in a
> >procedural assign whereas the text only permits "a single word
> >of a memory". The issues is whether something like:
> > reg [7:0] m [9:0][9:0];
> > initial m[5][5][3:0] = 0;
> >would be permitted. Clearly right hand uses of such a
> >select are fine.
> >
> >I don't know if the text is more exclusive than intended or
> >whether the grammar has a "cut and paste" error from the net
> >and/or expression side.
> >
> >If you can give me your read on this (today if at all possible)
> >I would really appreciate it.
> >
> >Gord.
> >--
> >----------------------------------------------------------------------
> >Gord Vreugdenhil gvreugde@synopsys.com
> >Staff Engineer, VCS (Verification Tech. Group) (503) 748-3054
> >Synopsys Inc., Beaverton OR
-- Shalom Bresticker Shalom.Bresticker@motorola.com Principal Staff Engineer Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478
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