From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Thu Apr 25 2002 - 09:38:40 PDT
Precedence: bulk
As Shalom and Steve Sharp have pointed out, this is old Verilog-1995
wording that should have been updated.
// This should be legal
reg [7:0] m [9:0][9:0];
initial m[5][5][3:0] = 0;
The text at the beginning of section 9.2 should be updated.
I'm sure this is not the last Verilog-1995 obsolete text that we will find
in the Verilog-2001 Standard
Regards - Cliff
At 12:07 AM 4/25/02 -0700, Stuart Sutherland wrote:
>Precedence: bulk
>
>Shalom, thanks for the detailed researching of the LRM on this.
>
>Cliff, as BTF chair, you should probably be the one to respond to the
>originator of the question with some semi-official position on what was
>intended to be allowed. And, of course, an errata should be filed, so
>that this can be officially clarified when we begin meeting again.
>
>Stu
>
>At 11:52 PM 4/24/2002, Shalom Bresticker wrote:
>>On further thought,
>>
>>I guess the reason that there is no explicit mention of writability is
>>that in Verilog-1995, both reads and writes of part-selects of memory
>>elements were not allowed, so that when we did allow array part-select
>>accesses in Verilog-2001, we also did not distinguish between reads and writes.
>>
>>Further strengthening that hypothesis is the fact that a Note at the end
>>of 4.2.2 mentioning the inability to access memory word bits was stricken
>>in Verilog-2001.
>>
>>And of course the fact that the new BNF does allow it.
>>
>>I think we can be pretty sure it is OK.
>>
>>It is unfortunate that there are no such examples in the LRM.
>>
>>Again, all the relevant sections of the LRM should be brought into alignment.
>>
>>Shalom
>>
>>
>>Shalom Bresticker wrote:
>>>While I also remembered that Verilog-2001 added the ability to do
>>>assignment to a bit-select or part-select of an array, I have been
>>>unable to find an explicit reference to this neither in the LRM itself
>>>nor in my email archives.
>>>
>>>Other relevant sections of the LRM are 3.10, 4.2, and Table 6-1.
>>>
>>>It is unfortunate that the texts relating to a single subject are spread
>>>out over 3 or 4 different places.
>>>It causes discrepancies. It also means that you read one section and are
>>>missing the supplemental information which appears in another section,
>>>you don't know you're missing it, and you don't even know where to look for it.
>>>
>>>The IEEE version doesn't even have an index or a detailed Table of Contents.
>>>
>>>Unfortunately, there are a lot of cases like this.
>>>
>>>Specifically with respect to this issue, it would be good to review
>>>every reference to "memory" in the LRM,
>>>and check whether it should be "memory" or "array", and check whether it
>>>is still accurate.
>>>
>>>What a headache !
>>>
>>>Shalom
>>>
>>>
>>>> >Date: Wed, 24 Apr 2002 11:56:05 -0700
>>>> >From: Gordon Vreugdenhil <gvreugde@synopsys.com>
>>>> >
>>>> >I ran into an apparent grammar/interpretation issue in the Verilog
>>>> >2001 LRM. The issue is a conflict between the grammars in Figs.
>>>> >9-1 and 9-2 versus the text at the beginning of 9.2. The grammar
>>>> >allows left hand side range selects on a memory/array in a
>>>> >procedural assign whereas the text only permits "a single word
>>>> >of a memory". The issues is whether something like:
>>>> > reg [7:0] m [9:0][9:0];
>>>> > initial m[5][5][3:0] = 0;
>>>> >would be permitted. Clearly right hand uses of such a
>>>> >select are fine.
>>>> >
>>>> >I don't know if the text is more exclusive than intended or
>>>> >whether the grammar has a "cut and paste" error from the net
>>>> >and/or expression side.
>>>> >
>>>> >If you can give me your read on this (today if at all possible)
>>>> >I would really appreciate it.
>>>> >
>>>> >Gord.
----------------------------------------------------
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