From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Thu May 02 2002 - 11:12:26 PDT
Precedence: bulk
At 09:41 PM 5/1/02 -0700, Paul Graham wrote:
>It turns out that an attribute is not allowed between the '@' and the
>opening '(' of the event list. So when you see '@' followed by '(*' you
>know it can't be an attribute. In my parser I have three separate
>productions to handle the wildcard sensitivity list:
>
> wildcard : '@' '*' | '@' '(*' ')' | '@' '(' '*' ')'
>
>It seems like a lot of work for a little piece of syntactic sugar!
>
>Paul
This enhancement is way more than syntactic sugar!
I have been showing this pending syntax for about four years in Verilog and
Advanced Verilog classes. I precede the discussion with examples of missing
and added sensitivity list entries for synthesizable code and the
pre-synthesis vs post-synthesis simulation mismatches that can be produced.
I discuss that adding more equations to the always block typically requires
more entries to the sensitivity list. Then I ask students what they would
think of a combinational sensitivity list written as @*? I always hear
"yeah"'s and "good"'s and occasionally a class break into spontaneous applause.
The @* not only reduces a bunch of redundant typing, it also prevents many
rtl-synthesis mismatch problems.
At HDLCon a year ago, Paul Menchini spoke in a session about VHDL-2001
enhancements and then I spoke about Verilog-2001 enhancements. During my
presentation, a VHDL-colleague of mine, Jim Lewis, leaned over to Paul and
told him that VHDL should add the @*. Jim told me that Paul said a process
* enhancement had been proposed but that some VHDL committee members were
able to defeat the proposal. I'm glad we passed the @* enhancement!
Just so people understand that this is more than just syntactic sugar
(albeit very nice syntactic sugar), during the Verilog-2001 vote, the
now-famous Cadence-6 who voted against the Verilog-2001 standard, listed
opposition to @* as one of their reasons for voting against the standard.
In a conference call to the Cadence-6, I explained the scope and value of
the @* which reduced opposition to this enhancement from 6 to 1 (the six
still voted no during the second ballot for other reasons).
I think this is one of the coolest enhancements added to the Verilog-2001
Standard. The three parser productions (four with the Dennis correction)
listed above is trivial compared to what we have required from Verilog
designers for years. Thanks, Mac, for proposing this enhancement during the
Verilog-2001 standards process!
I must admit, I do not get the same class enthusiasm when I show
Verilog-2001 attributes!
Regards - Cliff
----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, Synthesis and Verification Training
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