From: Adam Krolnik (krolnik@lsil.com)
Date: Thu May 09 2002 - 08:51:05 PDT
Precedence: bulk
Hi Jayaram;
>This indeed is getting interesting. So now
>there are two forms of include's (different syntax,
>identical meaning?):
>`include "a/b/c.d" -- a compiler directive
>include /a/b/c.d; -- include in a configuration
>From 13.2.2, it appears that the semantic meaning of the
>config-include is
>same as that of the include compiler directive. If so, what
>was the reason for the config-include?
There is a difference in the semantic meaning of the configuration
include. The difference lies in the fact that a configuration
included still processes relative file references from the
directory of the included configuration file.
For example:
% pwd
/user/krolnik/work/myproject
% cat lib.map
library project_lib
design/a/rtl/*.v,
...
-incdir design/a/rtl/, design/b/rtl/
;
// include technology library.
include /tech/library/verilog/tsmc/lib.map
% cat /tech/library/verilog/tsmc/lib.map
library tsmc_lib
src/verilog/*.v,
src/verilog/*/*.vlib,
-incdir src/verilog/...
;
The library project_lib should contain:
/user/krolnik/work/myproject/design/a/rtl/*.v
...
The library tsmc_lib should contain:
/tech/library/verilog/tsmc/src/verilog/*.v
/tech/library/verilog/tsmc/src/verilog/*/*.vlib
...
If one substituted
`include "/tech/library/verilog/tsmc/lib.map"
for the include statement, the tsmc_lib would be empty, because
these files don't exist:
/user/krolnik/work/myproject/src/verilog/*.v
/user/krolnik/work/myproject/src/verilog/*/*.v
I guess as a methodology note that `include is not recommended
in library definition files. They should be separate from any
verilog code so that one can maintain them independently of
the verilog source. It also makes it easier to write tools to
parse just them for source code locations.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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