From: Dennis Marsa (drm@xilinx.com)
Date: Thu May 09 2002 - 10:38:59 PDT
Precedence: bulk
Adam Krolnik wrote:
>
> Precedence: bulk
>
> Hi Jayaram;
>
> >This indeed is getting interesting. So now
> >there are two forms of include's (different syntax,
> >identical meaning?):
>
> >`include "a/b/c.d" -- a compiler directive
> >include /a/b/c.d; -- include in a configuration
>
> >From 13.2.2, it appears that the semantic meaning of the
> >config-include is
> >same as that of the include compiler directive. If so, what
> >was the reason for the config-include?
>
> There is a difference in the semantic meaning of the configuration
> include. The difference lies in the fact that a configuration
> included still processes relative file references from the
> directory of the included configuration file.
Is the term "configuration include" appropriate? Wouldn't
"library map include" be a better term?
I say this because the new kind of include is defined by
a BNF rule section A.1.1 titled "Library source text".
Configuration syntax is defined in section A.1.2 titled
"Configuration source text" and does not reference the new
BNF rule for library includes, so presumably one would have
to use the orignal `include directive in order to do includes
within a configuration?
> I guess as a methodology note that `include is not recommended
> in library definition files. They should be separate from any
> verilog code so that one can maintain them independently of
> the verilog source. It also makes it easier to write tools to
> parse just them for source code locations.
I don't see this made explicit anywhere in the standard, but
was it intended to allow library map definitions and/or
configurations to appear in the same source file as module
definitions?
Put another way, are the syntax for library maps (A.1.1) and
configurations (A.1.2) considered additions to the overall
verilog language, or separate companion languages?
What seems to make the most sense to me is that library map
syntax is really a separate companion language, but that
configuration syntax is an addition to the overall verilog
language.
Comments?
Dennis Marsa
Xilinx, Inc.
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