From: Adam Krolnik (krolnik@lsil.com)
Date: Fri May 10 2002 - 08:08:51 PDT
Precedence: bulk
:> I guess as a methodology note that `include is not recommended
:>in library definition files. They should be separate from any
:> verilog code so that one can maintain them independently of
:> the verilog source. It also makes it easier to write tools to
:> parse just them for source code locations.
:
:I don't see this made explicit anywhere in the standard,but
:was it intended to allow library map definitions and/or
:configurations to appear in the same source file as module
:definitions?
It was not explicitly forbidden, since we figured that someone
may want them together.
:Put another way, are the syntax for library maps (A.1.1) and
:configurations (A.1.2) considered additions to the overall
:verilog language, or separate companion languages?
:What seems to make the most sense to me is that library map
:syntax is really a separate companion language, but that
:configuration syntax is an addition to the overall verilog
:language.
This is format we have discussed, but have not explicitly stated.
The library file is meant as a replacement of the -f, -y, -v, etc.
command line options. One can use a library file (explicit or
implicitly specified) that defines where the sources are located.
One then uses a configuration to define what the system to be
compiled/simulated/etc. is to contain. Configurations can also
be used to specify subsets of a system (not just as the top level
system specification.)
This leaves out one thing, how to specify a location for precompiled
modules. This requires another file to hold this information
unfortunately for those tools that support this.
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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