From: Jayaram Bhasker (jbhasker@cadence.com)
Date: Fri May 17 2002 - 06:27:29 PDT
On generate statement:
My interpretation of this is slightly different. I believe the intent was to allow declarations only within the
generate scope - as specified in para 6 of 12.1.3. Sec 3.12 needs to be enhanced to include the generate scope.
Furthermore, such a generate block must have a generate_block_identifier (this rule is just like the other
begin..end blocks that require a label before you can have declarations within it).
- bhasker
-----Original Message-----
From: Shalom Bresticker [mailto:Shalom.Bresticker@motorola.com]
Sent: Sunday, May 12, 2002 8:31 AM
To: Paul Graham
Cc: btf@boyd.com
Subject: Re: questions about name spaces
Paul,
Regarding your second question.
I agree that the LRM is ambiguous about the case of an identifier declared in a generate statement which does not have a generate_block_identifier.
I interpret the LRM to say that "a wire declared within a generate statement lives in the scope of the module".
Shalom
Paul Graham wrote:
I have a couple of questions about name spaces.
1) Section 3.12 says:
The attribute name space is enclosed by the (*and *) constructs attached
to a language element (see 2.8). An attribute name can be defined and
used only in the attribute name space. Any other type of name cannot be
defined in this name space.
What does it mean to define an attribute name? Attribute names aren't really
defined, are they? Is the intent to say that an attribute name X bears no
relation to a name X declared in another space?
2) The more serious question. It is possible to declare an object, say a
wire, in a generate statement. Section 12.1.3, Generated instantiation,
says:
To support the interconnection between structural elements and/or
procedural blocks, generate statements permit the following Verilog data
types to be declared within the generate scope: ...
Does this mean that a wire declared within a generate statement lives in a
namespace specific to that generate statment? But note that section 3.12
does not list generate statements when it enumerates the possible name
spaces. This suggests that a declaration in a generate statements lives in
the scope of the containing module. This would result in something like:
module m;
parameter p = 1;
generate
if (p == 1)
wire x;
else if (p == 2)
reg x;
endgenerate
assign x = 1'b1;
endmodule
where you don't know until elaboration time whether x is a wire, a reg (in
which case the assignment is illegal) or is not declared at all.
If a wire declared within a generate statement lives in the scope of the
generate statement (instead of in the module scope) then this wire has no
hierarchical name, since there is no label on the generate statement.
If a wire declared within a generate statement lives in the scope of the
module, then it means that symbol table lookup cannot be done until
elaboration of the entire design, which is a large implementation burden.
For reference, in VHDL an object declared within a generate statement lives
in the scope of the generate statement. Furthermore, all VHDL generate
statements must be labeled, so that there is always a hierarchical pathname
to an object declared within a generate statement.
Paul
--Shalom Bresticker Shalom.Bresticker@motorola.com
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