From: Gordon Vreugdenhil (gvreugde@synopsys.com)
Date: Wed Jun 19 2002 - 09:12:36 PDT
Precedence: bulk
I recently talked with Cliff regarding 5 issues that have arisen
during work on implementing support for Verilog 2001 generate blocks.
Cliff suggested that I directly raise the issues with this group.
I've included one of the issues here and will raise the others in
separate notes.
A quick note about who I am: My name is Gord Vreugdenhil and I am an
R&D Staff Engineer at Synopsys in the VCS group. My background is in
Computer Science, with a Ph.D. in compiler design and optimization
from U.Waterloo in Canada. I previously worked at Analogy in Beaverton,
OR on an implementation of VHDL-AMS.
The first issue I would like to raise is regarding permissible values
for genvars.
LRM 12.1.3.1 currently reads: "...if the genvar is set to a negative
value, this shall be an error."
This means that the following example is illegal:
genvar i;
for (i = LAST-1; i >= 0; i = i - 1) begin :block
wire w;
end
The last assignment to "i", which causes the loop to
terminate, is an assignment of -1.
I think the intent was that negative values could not be used for an
actual instantiation of the block. I would like to propose that "if
the genvar is set to a negative value," be sticken and that a
paragraph be added in 12.1.3.1 that reads:
A genvar may contain a negative value as long as
such a value is a terminating condition for the
related loop and is not used as the index value for
an instantiation of the loop's named block.
Gord.
-- ---------------------------------------------------------------------- Gord Vreugdenhil gvreugde@synopsys.com Staff Engineer, VCS (Verification Tech. Group) (503) 547-6054 Synopsys Inc., Beaverton OR
This archive was generated by hypermail 2.1.4
: Mon Jul 08 2002 - 12:55:37 PDT
and
sponsored by Boyd Technology, Inc.