Verilog 2001 - Hierarchical names with generated identifier components

From: Gordon Vreugdenhil (gvreugde@synopsys.com)
Date: Thu Jun 20 2002 - 10:16:48 PDT


Precedence: bulk

Hierarchical names with generated identifier components

The LRM requires that the index in a generated identifier be a
sequence of digits (See LRM 2.7.2 and LRM 12.4, figure 12-7).
This disallows examples such as:

                genvar i;
                generate
                    for (i = 0; i < SIZE; i = i + 1) begin : b
                        wire w;
                        ....
                    end
                endgenerate

                assign b[SIZE-1].w = 1;

This seems to be a construct that should be allowed in a design.

Proposal:

Change 2.7.2 and/or 12.4 as follows:

        A generate identifier with an "index" component may
        have an elaboration time expression for the
        index, but such an expression must follow the
        same rules as those restricting the RHS of defparams.

This change could possibly just be folded into 12.4 (see
"Comment" below).

Implication: index expressions may use directly
    visible names (parameters, genvars, operators, etc)
    but would not be able to reference potentially
    unelaborated portions of the design.

Rationale: This permits virtually any reasonable design
    construct and avoids any issues regarding elaboration
    ordering, etc.

Comment: the use of "node name" in 2.7.2 isn't clear in the
    context of the grammar of 12.4. The text in 2.7.2 should
    either say that a generated identifier can be used in place
    of a "simple identifier" in 12.4 or additional rules should
    be added to 12.4 regarding a "node name". It appears that
    the text of 2.7.2 is redundant in terms of the structural
    composition of hierarchical identifiers in any case. I
    realize that there is a qualitative difference between
    a generated identifier that includes a dot or index component
    and a hierarchical name in which the dot or index component
    describes design hierarchy, but the intended impact of that
    distinction on hierarchical name composition is not clear.

Gord.

-- 
----------------------------------------------------------------------
Gord Vreugdenhil                                 gvreugde@synopsys.com
Staff Engineer, VCS (Verification Tech. Group)   (503) 547-6054
Synopsys Inc., Beaverton OR


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