From: Paul Graham (pgraham@cadence.com)
Date: Tue Jun 25 2002 - 19:21:37 PDT
Precedence: bulk
> Actually, a range type declaration would not have allowed things like
> triangular arrays of interconnected modules:
>
> genvar gv_i, gv_j;
> parameter TSIZE=16;
> generate
> for (gv_i =0; gv_i < TSIZE; gv_i = gv_i + 1) begin: idim
> for (gv_j = 0; gv_j < gv_i; gv_j = gv_j + 1) begin: jdim
> mod m(a[gv+i], b[gv_j], c[gv_i][gv_j]);
> end
> end
> endgenerate
Couldn't you have written:
generate
for gv_i[0:TSIZE-1]
for gv_j[0:gv_i-1]
mod m(...)
endgenerate
?
You might argue that [0:gv_i-1] is not a constant range, but since it
consists of constant expressions (treating a genvar as a constant) then it
is a constant range. It just gets reevaluated each time through the gv_i
loop.
Anyway, it was probably easiest to follow VHDL's example and base for
generates on for loops. Except in VHDL a for loop _is_ defined in terms of
a range. Compare
y := x(7 downto 0);
for i in 7 downto 0 loop ...
g1: for i in 7 downto 0 generate ...
Paul
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