Re: Verilog 2001 Issues - permissible genvar values

From: Michael McNamara (mac@verisity.com)
Date: Tue Jun 25 2002 - 21:29:32 PDT


Precedence: bulk

Michael McNamara writes:
>
> The inetent was that they would create a scope. At one point it was
> required that every generate key word be followed by a named block.
> Note that every generate loop DOES require a named begine block.
>

Sorry, I should not type just after I've been playing hockey. I meant
to say:

 The original intent was that generates would create a scope. At one
 point it was required that _every_ generate keyword be followed by a
 named block. This got relaxed to attempt to minimize too many useless
 scopes that might not create anything. Note that it is still the case
 that every generate loop DOES require a named begin block.

-mac



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