From: Michael McNamara (mac@verisity.com)
Date: Tue Jun 25 2002 - 21:26:45 PDT
Precedence: bulk
Paul Graham writes:
> > Actually, a range type declaration would not have allowed things like
> > triangular arrays of interconnected modules:
> >
> > genvar gv_i, gv_j;
> > parameter TSIZE=16;
> > generate
> > for (gv_i =0; gv_i < TSIZE; gv_i = gv_i + 1) begin: idim
> > for (gv_j = 0; gv_j < gv_i; gv_j = gv_j + 1) begin: jdim
> > mod m(a[gv+i], b[gv_j], c[gv_i][gv_j]);
> > end
> > end
> > endgenerate
>
> Couldn't you have written:
>
> generate
> for gv_i[0:TSIZE-1]
> for gv_j[0:gv_i-1]
> mod m(...)
> endgenerate
>
> ?
That syntax does express the same idea.
>
> You might argue that [0:gv_i-1] is not a constant range, but since it
> consists of constant expressions (treating a genvar as a constant) then it
> is a constant range. It just gets reevaluated each time through the gv_i
> loop.
>
> Anyway, it was probably easiest to follow VHDL's example and base for
> generates on for loops. Except in VHDL a for loop _is_ defined in terms of
> a range. Compare
>
> y := x(7 downto 0);
> for i in 7 downto 0 loop ...
> g1: for i in 7 downto 0 generate ...
>
> Paul
But by giving the user control over the iterator, Verilog does allow:
parameter END_I=16, END_J=32;
function integer f1(integer a) begin
f1 = ~(((a+3)^5)<<2)
end
function integer f2(integer a, b) begin
f2 = a < b? a+2 : (b*a)^6;
end
genvar gv_i, gv_j;
generate
for (gv_i=0; gv_i != END_I; gv_i = f1(gv_i)) begin: idim
for (gv_j = 0; gv_j != END_J; gv_j = f2(gv_j,gv_i)) begin: jdim
mod m(a[gv+i], b[gv_j], c[gv_i][gv_j]);
end
end
endgenerate
Pretty gnarly.
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