From: Michael McNamara (mac@verisity.com)
Date: Wed Jun 26 2002 - 08:50:01 PDT
Precedence: bulk
Gordon Vreugdenhil writes:
> Michael McNamara wrote:
> >
> > Precedence: bulk
> >
> > Michael McNamara writes:
> > >
> > > The inetent was that they would create a scope. At one point it was
> > > required that every generate key word be followed by a named block.
> > > Note that every generate loop DOES require a named begine block.
> > >
> >
> > Sorry, I should not type just after I've been playing hockey. I meant
> > to say:
>
> I understand. :-)
>
> > The original intent was that generates would create a scope. At one
> > point it was required that _every_ generate keyword be followed by a
> > named block. This got relaxed to attempt to minimize too many useless
> > scopes that might not create anything. Note that it is still the case
> > that every generate loop DOES require a named begin block.
>
> Right.
>
> So, back to intent. As far as I understand it, the main intent of
> allowing unnamed blocks in the first place is to allow conditional
> subdesign generation where the alternatives have the same name.
> That is fine, and an important design aspect.
>
> Why not do the following:
> 1) disallow module_or_generate_item_declaration in an unnamed block
> (except the implicit unnamed block for "generate" itself)
> 2) disallow unnamed blocks everywhere except in gen if/case alternatives
>
> This makes the grammar a bit longer, but probably makes the intent
> more clear. Many of the "silly" cases go away. The only downside
> that I can see is that it requires on to use a named block
> for a conditional declaration (ie. net, reg, function, task, etc).
> That may be a little bit restrictive, particularly for task/function
> declarations.
>
> Gord.
I believe your suggestion is verymuch on the right track.
Can you make the IEEE-1364 conference call today at noon? I am
kicking off the effort to gather on the errata of 1364-2001 into a
form we can publish.
The call in number is 1-800-314-2582
The passcode is 135467
-mac
>
> --
> ----------------------------------------------------------------------
> Gord Vreugdenhil gvreugde@synopsys.com
> Staff Engineer, VCS (Verification Tech. Group) (503) 547-6054
> Synopsys Inc., Beaverton OR
>
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