From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Wed Jun 26 2002 - 16:46:45 PDT
Precedence: bulk
There will soon be a new IEEE VSG ETF (Errata Task Force). When the ETF
reflector becomes active, I will quit sending this material to the BTF
reflector.
Per the IEEE-1364 Committee Meeting today, I was given an action item to
forward to the IEEE VSG a letter that I sent to the Accellera Board of
Directors on June 21, 2002. If the IEEE VSG would like to compose and send
a joint letter to the Accellera Board of Directors expressing a desire to
combine the Accellera and IEEE SystemVerilog efforts, this text may serve
as a good starting point. Please reply with comments and suggestions.
Regards - Cliff Cummings
=====
Subject 2: Accellera-IEEE Verilog Standards
2 - Accellera-IEEE Verilog Standards
I have deep concerns about the development of an Accellera SystemVerilog
3.1 Standard. I have expressed these concerns to both Dennis Brophy and
Vassilios Gerousis and would welcome their comments on this subject.
Specifically, I am concerned that the Accellera SystemVerilog committee
will exert significant effort to develop a SystemVerilog 3.1 Standard and
perhaps even other Accellera versions and then all of the work will be
re-debated and changed after the IEEE Verilog Standards Group takes over
work on the standard.
In short, the work will be done twice and it will change.
There is history to suggest this will happen. The OVI 2.0 Verilog Standard
was donated to the IEEE and even though the IEEE started from the donated
OVI Standard, we still changed significant portions of the standard,
removing some of the OVI proposed enhancements and adding others. The big
difference this time is that the IEEE Verilog Standards Group will not even
start with the Accellera SystemVerilog Standard, but will have to partition
the Accellera document into sections and insert them into the IEEE Verilog
Standard. This will certainly encourage changes during the merging process.
The only Accellera section that can be used without modification is the BNF
formal description annex, which started with the IEEE version of the BNF
and was enhanced.
I am excited by the enthusiasm shown by vendors to implement the Accellera
SystemVerilog 3.0 standard and want to continue this level of enthusiasm
among the vendors.
I am excited by the donations from EDA vendors of key technologies that I
believe could further enhance the SystemVerilog efforts. I look forward to
reviewing and incorporating many of those donations.
At the same time I do not want to debate all of the donations and proposed
enhancements twice and I doubt if the EDA vendors want to debate and defend
their work twice.
The question is, how do we maintain the enthusiasm and attention currently
shared by the EDA vendors and insure that the work will be done right, done
expeditiously and not significantly modified by the IEEE Verilog Standards
Group?
I submit for your consideration that the IEEE Verilog Standards Group be
encouraged to take over the Accellera document and merge it into the IEEE
Standard in the near future. I further suggest that all Accellera 3.1
efforts be moved to the IEEE Standardization process immediately and that
all enhancements be made to the IEEE Verilog Standard directly as opposed
to generating even more documentation that would eventually have to be
re-written and merged into the IEEE Standard.
I suggest that we find a new way of working with the IEEE that permits the
generation of Accellera checkpoint documents from the IEEE Verilog Standard
directly on an annual basis (for example, a SystemVerilog 3.1 Standard to
be delivered to the Accellera Board before DAC of next year) for use by
Accellera member companies to speed adoption of SystemVerilog enhancements.
The annual checkpoint documents would give companies a chance to
investigate and implement SystemVerilog enhancements and suggest changes
before the enhancements are cast in stone by the formal IEEE process. Mike
McNamara is the current chair of the IEEE 1364 Verilog Standards Group and
I suggest that he lead this effort and coordinate with the TC Chair,
Vassilios, to create the annual Accellera checkpoint documents.
This cooperative standards effort between Accellera and the IEEE would be
ground-breaking. Our hope is that this process would maintain the momentum
that has been generated by the Accellera committees and facilitate
implementation of an IEEE Verilog Standard that is better tested and more
quickly accepted than any of its predecessors.
I would welcome the opportunity to answer questions or share more ideas on
this subject with the Accellera Board, if requested.
Best Regards - Cliff Cummings
Member of the SystemVerilog Committee
Past Chair of the IEEE Verilog-2001 Behavioral Task Force
Member of the IEEE Verilog-1995 and Verilog-2001 Standards Groups
----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, Synthesis and Verification Training
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