From: Clifford E. Cummings (firstname.lastname@example.org)
Date: Thu Jun 27 2002 - 14:38:54 PDT
Your questions and points are good ones so I am going to send the response
to the BTF reflector so others can consider the points. Hope that is okay
Regards - Cliff
At 01:26 PM 6/27/02 -0700, you wrote:
> > Specifically, I am concerned that the Accellera SystemVerilog committee
> > will exert significant effort to develop a SystemVerilog 3.1 Standard and
> > perhaps even other Accellera versions and then all of the work will be
> > re-debated and changed after the IEEE Verilog Standards Group takes over
> > work on the standard.
> > In short, the work will be done twice and it will change.
>What's wrong with that? Look at all the review going on in the btf
>regarding generate statements. Clearly they weren't fully thought out at
>the time they were voted in by the IEEE. Having IEEE review, and possibly
>change, what Accellera proposes would be a good thing.
If the changes are corrections or clarifications, I agree that the changes
would be a good thing. If the changes are scrapping functionality in favor
of different functionality I think this is bad and will hinder adoption of
Would you implement new Accellera functionality knowing that the IEEE
committee may delete the functionality in favor on incompatible IEEE additions?
I believe corrections and clarifications will come as vendors implement the
Accellera checkpoint documents, something we never had with the
The problem with adding enhancements to standards is that most enhancements
are never tested until they become standardized. We would have welcomed any
EDA vendor actually implementing the Verilog-2001 enhancements as they were
being proposed but it is a chicken-and-egg scenario: no vendor wants to
exert effort on an enhancement until it has passed and we don't know if we
adequately and fully described the enhancement until a vendor tries to
implement it. I am hoping for this type of hybrid standards development by
doing the work in an IEEE committee and then designate annual pass-lists
(Accellera checkpoint documents) that vendors can start to implement and
discover the problems or ambiguities until the final IEEE document is ready
for the next cast-in-stone vote.
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
email@example.com / www.sunburst-design.com
Expert Verilog, Synthesis and Verification Training
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