Re: Accellera-IEEE Verilog Standards Statement - Paul Graham's questions

From: Adam Krolnik (krolnik@lsil.com)
Date: Thu Jun 27 2002 - 14:58:56 PDT

Precedence: bulk

Hi Cliff, Paul;

Paul writes:

>If the changes are corrections or clarifications, I agree that the changes
>would be a good thing. If the changes are scrapping functionality in favor
>of different functionality I think this is bad and will hinder adoption of
>a standard.

I don't know about scrapping functionality in favor of different
functionality,
but people have expressed reservations about including certain elements
of
systemVerilog into IEEE1364.

It will be interesting to see what happens with the current spec and the
desire to put out a SystemVerilog 3.1 spec.

  THanks.

   Adam Krolnik
   Verification Mgr.
   LSI Logic Corp.
   Plano TX. 75074

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