A proposal for variable width floating point in Verilog 200X

From: Kurt Baty (kurt@wsfdb.wsfdb.com)
Date: Wed Mar 05 2003 - 05:58:20 PST

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    A proposal for variable width floating point in Verilog 200X

    The work on a floating point standard for both VHDL and Verilog
    http://www.eda.org/fphdl/

    Which is in turn based on IEEE754
    http://grouper.ieee.org/groups/754/

    This work has produced a reference proposal which gets the same
    answer(bits!) in IEEE754, VHDL and Verilog!

    key verilog files are:

            fphdl_real_functions.inc
                    fphdl64_real_functions_base.inc
                    fphdl_convert_functions.inc

    The variable width floating point number are defined as bit range
    [exponent_width:-fraction_width] to define the exponent and the
    mantissa/fraction of a floating point number. For a 32 bit
    representation that makes the number look as follows:

    0 00000000 0000000000000000000000
    8 7 0 -1 -23
    +/- exp. fraction

    Where the sign is bit 8, the exponent is bits 7-0 (8 bits) with bit 7
    being the MSB, and the mantissa is bits -1 - -23 (-1-23 = 24 bits)
    where bit -1 is assumed to be the MSB.

    floating point implementation of almost any length can be made by
    using this specification. You need to adhear to the following
    constraint, the number must be 7 wide or greater, with at least a
    3 bit exponent and also least a 3 bit fraction.

    SO, what would verilog with variable width floating point numbers
    look like:

    note that:

    wire signed [7:0] a;
    reg signed [15:0] b;

    where:

    reg signed [31:0] c;

    is functional the same as:

    integer c;

    SO:

    wire float [3:-4] a;
    reg float [7:-8] b;

    where:

    reg float [11:-52] c; // IEEE 64 bit floating point

    is functional the same as:

    real c; // IEEE 64 bit floating point
     
     
    ALSO:

    wire complex [3:-4] a;
    reg complex [7:-8] b;
    reg complex [11:-52] c;

    STILL OTHERS:

    wire fixed [4:-4] a;

    reg polar [6:-7] b;

    This plan only change the info on the wire/reg bits!

    There still lots to discuse.

            Kurt Baty

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