Minutes of BTF Meeting May 19, 2003

From: Steven Sharp (sharp@cadence.com)
Date: Mon May 19 2003 - 15:48:17 PDT

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    Minutes of BTF Meeting May 19, 2003

    Meeting started at around 10:30 PST

    In attendance:
            Steven Sharp
            Karen Pieper
            Stefen Boyd
            Kurt Baty
            Michael McNamara

    Discussion of Kurt's power operator proposal for ETF occupied early part
    of meeting time. When it moved into new float and complex types, discussion
    was stopped and BTF meeting was called to order. The starting topic was
    determining which enhancement requests to the ETF had champions and should
    be considered for addition by the BTF. With few of the originators of the
    requests present, the following items were discussed:

      Issue 287 - `compatibility - backward compatibility compiler directives

    It was generally agreed that it would be valuable to have some kind of
    standard mechanism for compiling older code that would not compile in newer
    versions of the language (mostly due to new reserved keywords). Stefen
    suggested attributes attached to modules, or something in configs to
    control this. Steven pointed out that attributes and configs are things
    that might be turned off in Verilog-1995 mode. In particular, configs
    contain new keywords that would need to be turned off for full backward
    compatibility.

    Steven raised a separate issue that new keywords in configs are a severe
    backward compatibility issue, which could be eliminated by deprecating
    configs in Verilog source files and only allowing them in the library
    mapping files. Steven will file this as a separate issue.

    There was some further discussion of a compatibility mechanism, which was
    eventually stopped with the agreement that this issue was important enough
    to consider an addition to the standard.

      Issue 293 - variable width floating point in Verilog 200X

    Kurt Baty is strongly in favor of this proposal. He does acknowledge that
    it might only be useful to him and a small group of other designers. This
    should be raised at DAC to find out whether use would be widespread enough
    to justify adding it to the language. A second issue is how this would fit
    into the rest of the type system. There was some discussion of whether the
    data types should be made orthogonal to the resolution semantics (variable
    versus various net types). This is also applicable to any other new types.
    If Kurt's new specific types are not added to the language, he would like
    some new general mechanism added that could be used to support the same
    functionality (e.g. with structs and functions).

      Issue 62 - add record/structure data type

    There was some discussion about whether Accellera would be donating the
    SystemVerilog content to IEEE 1364. There was also discussion of the fact
    that the new SystemVerilog data types are all variables and whether it was
    important to make them orthogonal and allow them for nets also. This is
    another issue that should be raised at DAC.

      Issue 61 - add enumerated data type

    This is in a similar category to issue 62 above.

      Issue ?? - automatic connection of matching names

    Kurt brought up another SystemVerilog feature that would be convenient,
    which is the .* mechanism for automatically connecting instance ports
    to signals of the same name, without explicitly specifying each connection.
    This should be filed as an enhancement request. If the SystemVerilog
    content is not donated to the IEEE, a proposal will be needed also.

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