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From: Jay Lawrence (lawrence@cadence.com)
Date: Tue Jun 03 2003 - 07:15:36 PDT

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    To members of the IEEE-1364 working groups:

    Yesterday Cadence announced that we are donating 3 technologies to the
    IEEE-1364 working group. These are being delivered to the offices of the
    IEEE today including the official letters releasing the reprint rights
    and stating that there are no known patents involved in this donation on
    behalf of Cadence.

    I sent all the documents to the reflector yesterday however limitations
    on size prevented them from being distributed. Each of these has now
    been added as an enhancement and the content uploaded to boyd.com. You
    can follow the link below to get to the enhancement. Each includes a
    link to the actual donated document.

    Briefly, the contents includes:

    - A proposal on extending Verilog data types on all object kinds
    including: variables, nets, ports, task/function arguments and
    parameters. This includes enums, vectors, structs, and arrays. It also
    contains details on how dynamic memory allocation of all these types
    works.

    http://boyd.com/1364_btf/report/full_pr/357.html

    - A series of system tasks for randomizing and constraining Verilog
    variables of all types. This donation also has a reference
    implementation that will be available for free download and will work
    with any VPI compliant simulator.

    http://boyd.com/1364_btf/report/full_pr/359.html

    - A file format specification for vendor-independent IP encryption. This
    uses standard algorithms and digital envelope theory to provide a
    standard secure format for the distribution of Verilog models. This
    technology is available in Q3 release of Incisive and is immediately
    available for Beta.

    http://boyd.com/1364_btf/report/full_pr/358.html

    Cadence looks forward to working through this donation and any others
    that come before the 1364 committee to produce a robust, open,
    next-generation Verilog.

    Sincerely,

    Jay Lawrence

    ===================================
    Jay Lawrence
    Senior Architect
    Functional Verification
    Cadence Design Systems, Inc.
    (978) 262-6294
    lawrence@cadence.com
    ===================================

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