Verilog Standards Group meeting Tuesday June 24th

From: Michael McNamara (mac@verisity.com)
Date: Tue Jun 17 2003 - 14:46:53 PDT

  • Next message: Stefen Boyd: "enhancement/359: constraint library"

    Precedence: bulk

           We will hold a IEEE-1364 Verilog Standards Group meeting on
           Tuesday, June 24th, at 8:30 am pacific time. Those needing
           call in details please send email to vsg@verilog.com

           The agenda is to consider for approval the 52 ETF passed
           issues, which you are encoraged to review at the web site
           http://www.boyd.com/1364_btf/report/etfpassed.html

           Also at this meeting, commencing at 9:00 am, the committee will
           discuss on going work on the 1364-2005 PAR, including the
           donations we have already received, and further donations we
           might receive.

           Michael McNamara



    This archive was generated by hypermail 2.1.4 : Tue Jun 17 2003 - 14:49:52 PDT and
    sponsored by Boyd Technology, Inc.