operator overloading

From: Kurt Baty (kurt@wsfdb.wsfdb.com)
Date: Thu Jul 17 2003 - 08:35:45 PDT

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    > Kurt suggested that the math functions from AMS be implemented as some
    > kind of Verilog packages. Almost all of the AMS routines are already
    > covered in Kurt's variable width floating point libraries. However, if
    > the types are not built-in, then they could not be used with infix
    > operators without something like operator overloading. Gord pointed out
    > that there would be serious problems integrating operator or function
    > overloading with Verilog's type system.
    >

    I am interrested in understanding what these "serious problems" are,
    If it is just hard work to do this, you need to understand that the
    overloading is not even close to free (of work) in VHDL.

            thanks

            kurt

    Witness this latest fphdl e-mail David Bishop:

    > From owner-fphdl@eda.org Wed Jul 16 08:39:14 2003
    > Date: Wed, 16 Jul 2003 09:45:40 -0400
    > From: David Bishop <david.bishop@kodak.com>
    > X-Accept-Language: en
    > MIME-Version: 1.0
    > To: fphdl@eda.org
    > Subject: floating point VHDL Package overloads
    > Content-Transfer-Encoding: 7bit
    >
    >
    > A basic question has come up as to what overloaded should be included in the
    > VHDL
    > floating point packages. In the list below, I have overloaded for real,
    > integer,
    > signed, and unsigned. For complex numbers I have only overloaded for
    > floating_point.
    >
    > This causes a problem. When you do the following:
    > signal X, Y : fp32;
    > X <= Y + "0000000000000110";
    > The compiler does not know how to interperate the constant. Should it do it as
    > a fp32, signed, or unsigned? Because of this I plan to eliminate the "signed"
    > and
    > "unsigned" overload operations. However, is this something important enough so
    > that I should make the uses live with the type caseing?
    >
    > You could do:
    > X <= Y + unsigned'("0000000000001100");
    > everywhere, but would that be worse than:
    > X <= Y + to_fp32 (unsigned'("0000000000001100"));
    > or
    > X <= Y + to_integer (unsigned'("0000000000001100"));
    > (assuming we leave integer and real overloading)
    > What does everybody think?
    >
    >
    > function "+" (
    > l, r : fp32) -- floating point 32 bit input
    > return fp32;
    >
    > function "+" (
    > l : fp32; -- floating point 32 bit input
    > r : real)
    > return fp32;
    >
    > function "+" (
    > l : real; -- floating point 32 bit input
    > r : fp32)
    > return fp32;
    >
    > function "+" (
    > l : fp32; -- floating point 32 bit input
    > r : integer)
    > return fp32;
    >
    > function "+" (
    > l : integer; -- floating point 32 bit input
    > r : fp32)
    > return fp32;
    >
    > function "+" (
    > l : signed; -- floating point 32 bit input
    > r : fp32)
    > return fp32;
    >
    > function "+" (
    > l : fp32; -- floating point 32 bit input
    > r : signed)
    > return fp32;
    >
    > function "+" (
    > l : unsigned; -- floating point 32 bit input
    > r : fp32)
    > return fp32;
    >
    > function "+" (
    > l : fp32; -- floating point 32 bit input
    > r : unsigned)
    > return fp32;
    >
    > function "+" (
    > l, r : complex_fp32) -- complex floating point 32 bit input
    > return complex_fp32;
    >
    > function "+" (
    > l : complex_fp32; -- complex floating point 32 bit input
    > r : fp32 )
    > return complex_fp32;
    >
    > function "+" (
    > l : fp32;
    > r : complex_fp32) -- complex floating point 32 bit input
    > return complex_fp32;
    >
    >
    > --
    > David W. Bishop dbishop@vhdl.org
    >
    >
    >

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