Re: EETimes article "Verilog schism looms"

From: Alec Stanculescu (alec@fintronic.com)
Date: Thu Sep 04 2003 - 12:25:32 PDT

  • Next message: Michael McNamara: "Minutes of the August 25th meeting of the IEEE Verilog WG"

    Precedence: bulk

    Karen,

    > Mac,
    >
    > Having experienced standards committee wars in the past (OVI vs VI, CFI vs
    > OVI, ...), I strongly recommend that you not create a war in the press
    > between IEEE and Accellera. It is unproductive and disruptive. Synopsys
    > and many other EDA companies are supportive of both organizations and the
    > processes that they have defined for producing standards. We will work to
    > ensure smooth operations within and between IEEE and Accellera.
    >
    > Regards,
    > Karen
    >
    >
    > ___________________________________________________________________
    > Karen Bartleson
    > Director, Quality and Interoperability
    > Synopsys, Inc.
    > phone: 719-528-5467 (Colorado Springs, CO)
    > fax: 719-533-0209 (Colorado Springs, CO)
    > phone: 650-584-4840 (Mountain View, CA)
    > fax: 650-584-4102 (Mountain View, CA)
    > mobile: 719-330-6727 (anywhere, USA)
    >

    Your e-mail to Mac is encouraging to all of us. The only possible
    improvement that I see is that perhaps it should have been addressed to more
    people than just to Mac, such as "Dear Standardization Friends and
    Colleagues". Indeed, wars are bad for everyone.

    In spite of many details that are perhaps debated more than they deserve, we
    should not loose track of the global picture:

    1. The IEEE 1364 has done a tremendous job over many years in
       releasing both Verilog 1995 and Verilog 2001.

    2. The chair of IEEE 1364 has had to make several difficult decisions.
    In 2001, Mac made the decision to encourage the members of the IEEE 1364 to
    take a leave of absence and participate in the work done at Accellera
    on adopting various donations. This decision was made based on
    promises made by Accellera and others that the resulting work will be
    donated to IEEE in 2002. This "deadline" was extended to June 2003,
    in order to make it possible for Accellera to donate SystemVerilog 3.1
    rather than 3.0.

    Mac was criticized by some people for delaying for such a
    long time the work done by the IEEE 1364 Committee. He is being
    criticized now for sticking to a deadline. The truth is that he, as
    Chair of the IEEE 1364 Committee, has to make some hard decisions for this
    Committee to be able to function properly.

    3. There is a co-ordination group within the IEEE 1364 Committee,
    whose Chair I have been elected, that will consider donations made to
    the IEEE for extending the Verilog language. This group will start
    working and it is good that it will start working very soon. It will
    obviously work only on donations that have been submitted
    already. While the work has not started yet it is possible that Mac
    may not refuse donations that are past the August 1st deadline.

    However, the August 1st deadline will harden quickly in time and at some
    point, after significant work will be done on inclusion of the
    existing donations into Verilog 2005, new donations will be
    accepted, but only for inclusion in Verilog 2010.

    I look forward to your support for the IEEE 1364, as well as for
    Accellera.

    Best regards,

    Alec Stanculescu

    This archive was generated by hypermail 2.1.4 : Thu Sep 04 2003 - 13:26:03 PDT and
    sponsored by Boyd Technology, Inc.