Committment to assign Copyright of System Verilog to IEEE-1364

From: Michael McNamara (mac@verisity.com)
Date: Thu Oct 16 2003 - 13:24:25 PDT

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    The Board of Accellera has approved a press release which will be
    covered by the EETimes OnLine <http://www.eetimes.com> tomorrow,
    Firday, October 17th, where in Accellera says:

    'In the coming year, Accellera plans to enhance the process it uses to
    build and maintain electronic design standards with the IEEE and
    assign copyright of SystemVerilog 3.1a to the IEEE for stanardization
    consideration by the IEEE 1364 Working Group before the 41st Design
    Automation conference.'

    Personally, I feel that it is indeed great news that Accellera is
    committing itself to this action, and to a timetable for the action.

    I propose that we discuss in the Monday, October 20th IEEE-1364
    conference call (8:30 am Pacific time) what this committment means to
    our project.

     Michael McNamara, Chairman, IEEE 1364 Working Group <mac@verilog.com>
                       Sr VP Technology, Verisity Design <mac@verisity.com>
                       W 650-934-6888 F 650-934-6893 M 408-930-6875

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