Re: Enhancement: Dynamic Values on attributes.

From: Steven Sharp (sharp@cadence.com)
Date: Thu Oct 30 2003 - 15:31:18 PST

  • Next message: Krishna Garlapati: "Re: Enhancement: Dynamic Values on attributes."

    In Verilog-2001, attribute values can already be set using constant
    expressions. This allows them to be defined in terms of compile time
    constants such as parameters and genvars. They can even use constant
    functions to compute things that are not easily done with expressions.
    This would appear to provide the basic functionality that you are
    talking about. I am not aware of any tools that support anything but
    simple constants for attribute values (and some apparently only accept
    strings), but that is not the fault of the 2001 standard.

    Beyond this, what you are proposing effectively involves two extensions.
    The first is to allow certain system functions to be used in constant
    expressions. This is already mentioned in a couple of the proposals
    that I have made. This seems reasonable for system functions that are
    "pure" functions.

    The second is a new standard system function called $strcat, which works
    much like $swrite but is a function instead of a task (so it could be
    used in constant expressions).

    While neither of these is unreasonable, I don't think that the solution
    to your particular problem requires them. The reason it appears to be
    needed is that the genvars or parameters that you want to use to set
    the values are numerical values. But your tool has defined a set of
    attributes that it expects to be set using string values, with numbers
    encoded as sequences of characters. "Printing" a numerical value into
    a string form is a complex operation, and your proposal is to do this
    with a system function.

    But there is a simpler solution to this. The only reason for this
    complex operation is that you chose to define the attributes for your
    tool to expect strings instead of numerical values. It just isn't a
    very convenient format for values you want to compute numerically. If
    you redefined the attributes to be numerical values instead, then
    this would all become simple to do in Verilog-2001. If you need to
    maintain backward compatibility, you could accept either the old
    attribute values which are strings, or the new ones which are numbers.

    From your example, it appears that "xc_rloc" takes a string that
    holds a row and column position encoded by strings of digits after
    "R" and "C" (I'll ignore the ".S" part, since I didn't understand what
    it was). You could do the same thing easily in Verilog-2001 by changing
    this to two attributes, "xc_rloc_R" and "xc_rloc_C", which take the
    row and column directly as numerical values instead of converted to
    strings. Then your example would become

    generate for(i=0; i <= 7; i = i+1)
      begin: my_reg
        (* xc_rloc_R=i, xc_rloc_C=0, xc_uset="SET1" *) FDE flip_flop
    (.D(d[i]), .CE(ce),.C(clk),.Q(qb[i]));
      // myreg0.flip_flop gets an attribute xc_rloc_R = 0
      // myreg0.flip_flop gets xc_rloc_R = 1
      // and so on...
      end
    endgenerate

    This works fine with the existing Verilog-2001 language. You just
    have to implement attributes fully as defined, and then change the
    attributes that your tool uses.

    It is possible that I am missing something here. Someone recently
    posted a question of how to do something like this in comp.lang.verilog.
    I answered with a description of 2001 attributes, and how the tool
    vendor could redefine their attributes to make this work, and I got
    flamed for my efforts.

    Steven Sharp
    sharp@cadence.com

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