From: Adam Krolnik (krolnik@lsil.com)
Date: Fri Oct 31 2003 - 11:11:35 PST
Hi Krishna;
>Looks like System Verilog does it nicely. But how does the tool
>figure out that you are dealing with strings in parameter unless
It's not clear as to what is supposed to happen. I will ask...
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
Co-author "Assertion Based Design"
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