From: Adam Krolnik (krolnik@lsil.com)
Date: Mon Nov 03 2003 - 06:29:33 PST
Hi Krishna;
>But how does the tool figure out that you are dealing with strings in
>parameter unless the declaration was :
>parameter string astr = {"R",8'h30 + i,"C0.S0"}; // i=2 => astr=R2C0.S0
Each element is sized and then concatenated, just like verilog 1995.
This line (below) is verilog-1995. You can do this today in VCS.
The program I included compiles in VCS with the +v2k option
for attributes.
parameter astr = {"R",8'h30 + i,"C0.S0"}; // i=2 => astr=R2C0.S0
module test;
parameter astr = {"R",8'h30 + 8'd2,"C0.S0"};
//(* astr = {"R",8'h30 + 8'd2,"C0.S0"} *)
(* astr = astr *)
reg adam;
initial $display("astr parameter is %s.\n", astr);
endmodule
% vcs catstr.v
...
Parsing design file '/tmp/catstr.v'
Top Level Modules:
test
No TimeScale specified
1 unique modules to generate
Invoking loader...
Chronologic VCS simulator copyright 1991-2003
Contains Synopsys proprietary information.
Compiler version 7.0.1; Runtime version 7.0.1; Nov 3 08:27 2003
astr parameter is R2C0.S0.
V C S S i m u l a t i o n R e p o r t
Adam Krolnik
Verification Mgr.
LSI Logic Corp.
Plano TX. 75074
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