Re: Enhancement: Dynamic Values on attributes.

From: Krishna Garlapati (krishna@synplicity.com)
Date: Mon Nov 03 2003 - 11:02:11 PST

  • Next message: Adam Krolnik: "Re: Enhancement: Dynamic Values on attributes."

    Hi Adam,
     
     Your example works for direct connstants (like 1+2) within parameters.
    But I don't think it will, when used in conjunction with variables that
    are constants
    at compile time (like genvars).

    genvar i;

    generate for(i=0; i<=7; i = i + 1)...

    parameter xc_rloc = {"R", i, "C0.S0"};
    (* xc_rloc = xc_rloc *) foo bar(..port connections..)
    ..
    ..
    endgenerate

    In this example it is not clear which value of i would be binded to the
    the parameter
    declaration for xc_rloc. Moreover, I think parameter declarations are
    illegal within
    generates, they can only be overrided.

    I still think there is a need for a builtin constant function in Verilog
    that produces
    a concatenated string output on compile time constant values.

    Thanks,

    - Krishna.

    Adam Krolnik wrote:

    >
    > Hi Krishna;
    >
    > >But how does the tool figure out that you are dealing with strings in
    > >parameter unless the declaration was :
    >
    > >parameter string astr = {"R",8'h30 + i,"C0.S0"}; // i=2 => astr=R2C0.S0
    >
    > Each element is sized and then concatenated, just like verilog 1995.
    > This line (below) is verilog-1995. You can do this today in VCS.
    > The program I included compiles in VCS with the +v2k option
    > for attributes.
    >
    > parameter astr = {"R",8'h30 + i,"C0.S0"}; // i=2 => astr=R2C0.S0
    >
    >
    > module test;
    >
    > parameter astr = {"R",8'h30 + 8'd2,"C0.S0"};
    > //(* astr = {"R",8'h30 + 8'd2,"C0.S0"} *)
    > (* astr = astr *)
    > reg adam;
    > initial $display("astr parameter is %s.\n", astr);
    >
    > endmodule
    >
    > % vcs catstr.v
    > ...
    > Parsing design file '/tmp/catstr.v'
    > Top Level Modules:
    > test
    > No TimeScale specified
    > 1 unique modules to generate
    > Invoking loader...
    > Chronologic VCS simulator copyright 1991-2003
    > Contains Synopsys proprietary information.
    > Compiler version 7.0.1; Runtime version 7.0.1; Nov 3 08:27 2003
    >
    > astr parameter is R2C0.S0.
    >
    > V C S S i m u l a t i o n R e p o r t
    >
    >
    > Adam Krolnik
    > Verification Mgr.
    > LSI Logic Corp.
    > Plano TX. 75074
    >
    >
    > 

    -- 
- Krishna Garlapati, Synplicity Inc. (408)215-6152

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