From: Brad Pierce (Brad.Pierce@synopsys.com)
Date: Fri Nov 21 2003 - 10:43:33 PST
Meeting started at 10:40 Pacific Time
In attendance:
Steven Sharp
Kathy McKinley
Mehdi Mohtashemi
Karen Pieper
Brad Pierce
Keith Gover
Ennis Hawk
Kurt Baty
Stuart Sutherland
Francoise Martinolle
Tom Fitzpatrick
Cliff Cummings
Steven Dovich
Alec Stanculescu
Mehdi moves, Kurt seconds accepting minutes. No opposed, no abstain.
Shalom points out that the registration page at http://www.verilog.com
requires an IEEE number. Mac says it will work using 'none'. Kurt notes
that ACM/IEEE membership is interchangeable for the standards committees.
Steve Dovich reports on the IP Encryption task force, noting that he has a
few more volunteers (Richard Ho, Alec Stanculescu and Bernie Delay) and that
the task force will soon be working out a schedule.
Kathy reports on the Extensions Guidelines task force, noting that they met
last week and further discussion continues via e-mail. Target completion
date is Dec. 15. Mac wants to dial in, too. Its meetings will now be at
8:30 am Pacific/11:30 Eastern on the Mondays without VSG meetings.
Alec not yet on call, so no report from the Coordination committee. Steven
summarizes what was said at VSG meeting. Mac asks what the BTF dates are.
Kathy and Kurt say will have internal draft proposals by next Monday, then
will have a draft for review by BTF by Dec. 15.
Kurt asks whether we need a discussion on packages, overloading, data types,
and the other high-priority items according to user surveys and according to
dependency list. He phoned into a SV-BC face-to-face to discuss the
proposals they approved for packages and overloading. He assumes BTF will
adopt something like them, too. He told SV-BC that the proposals didn't go
far enough to fully support his floating-point standards work. He thinks we
can eventually do better than VHDL, but feels we are still missing some
things, e.g., introspective types on function inputs instead of requiring
widths to be defined exactly in advance. Needs unconstrained objects.
Someone has concerns about us working on this stuff if too much interaction
with the likely SV donation.
Kathy asks, is Kurt really asking for requirements development? Kurt, yes,
and that we need development of requirements examples that are 100's of
lines long, as requirements, and he volunteers to do so. He says he's not a
language guru, so he'd like some feedback on his language ideas. Suggests
forming another subgroup, instead of "boring" the entire BTF phone call.
Wants to begin his enhancements where SystemVerilog leaves off.
Steven Sharp thinks that Kurt has a good point about the dependency on data
types. Someone asks, aren't the SV 3.1A data types the same as in SV 3.1?
Francoise says, yes, and they have been fairly stable even since SV 3.0.
Kurt wants unconstrained data types, perhaps parameterized data types.
Part of the charter of BTF is said to be requirements for functionality that
goes beyond SystemVerilog. Tom wants it to be upward compatible with
SystemVerilog. Kurt has no problem with that. Kathy says we should develop
full set of requirements independently of SystemVerilog. Kurt agrees.
Steven says were extending the IEEE standard, not extending SystemVerilog.
Kurt is assuming that we will adopt SystemVerilog data types, or that we'll
end up doing something similar, so it would be better to get started now in
parallel under the assumption that the data types will be roughly like
SystemVerilog. Steven says we need to make progress, and that it would be
better to start with requirements, and only then work out specific language
features.
Steven asks, should we form a committee about that? He thinks it's a little
premature. Kurt thinks there are substantial discussions to hold in this
space. Steven suggests people become familiar with both the Accellera data
types and the Cadence data type donation. Brad notes it's hard to view the
Cadence donation on line.
Action Item: Mac to make direct links to the 9 donations on the
www.verilog.com/1364 page.
Kurt thinks there are not really so many conflicts between the SystemVerilog
data types and the Cadence data type proposal, but Steven and Kathy suggest
there are indeed some important implications that need to be considered.
Steven repeats advice to 'get up to speed' on the two data type systems.
Kurt says there are a lot of intertwined issues with packages, function
introspection, etc. that need to be discussed.
Not taking any immediate action on the data type issue.
Steven says there are some revisions needed to Cadence data type proposal.
Kathy says some cleanup is needed, especially on the pointer-like types. A
new version should be available in December. Kurt thinks clarification is
needed. He will read through, write up response and e-mail. Kathy is owner
of document, and asks to be sure that any issues/clarification requests get
sent to her.
Action items: Kurt to send feedback about Cadence data type proposal.
Kathy to have revised version of data type proposal available by the end of
2003.
Alec joins conference. Gives summary of Coordination committee. Says
initial emphasis should be on encryption and data types. Other task forces
include ones on classes and predefined classes, verification, aspect
programming, generic interconnect, separate compilation, transaction
recording, VPI. Some overlap amongst task forces and with Accellera.
Steven says the consensus is that data type dependency is fundamental but he
feels a task force on it would still be a little premature. Alec says it's
not too early to clarify what is there already, not to propose new
constructs, but just to clarify what is in V2K. Steven says that is an ETF
issue. But Alec says it's beyond that. Says SystemVerilog has problems.
Brad says any problems should be forwarded to Accellera and asks what they
are. Alec says difference between reg and wires and issues raised by
Cliff's presentation about interfaces at the SystemVerilog face-to-face on
Nov. 14, 2003.
Alec moves to form separate compilation task force. Discussion about the
goals of proposed task force. Problems that anyone will have because they
are inherent in Verilog 2001. Ennis Hawk seconds. Not specifically about
packages. Alec says no conflict with SystemVerilog.
Cliff suggests tabling until next meeting. So Steven postpones vote until
further discussion.
Meeting adjourned.
This archive was generated by hypermail 2.1.4
: Fri Nov 21 2003 - 10:35:32 PST
and
sponsored by Boyd Technology, Inc.