A big Thank You for all of your effort of 1364-2001 Version C

From: Michael McNamara (mac@verisity.com)
Date: Fri Dec 19 2003 - 14:40:03 PST

  • Next message: Francoise Martinolle: "Re: draft of Process Flow Specification"

    -- On Dec 19 2003 at 09:43, k.mccabe@ieee.org sent a message:
    > To: standards-staff@majordomo.ieee.org, mac@verisity.com, mbratnick@corecompr.com, d.schiff@ieee.org
    > Subject: "IEEE 1384(TM) news item"
    > Hi,
    > The following news release is being disseminated today to the trades/media
    > covering computer technology, electronics and semiconductors.
    >
    > ***
    >
    > Contact: Michael McNamara, Chair, IEEE 1364(TM) Working Group
    > +1 650-934-6888, mac@verisity.com
    > or
    > Karen McCabe, IEEE Senior Marketing Manager
    > +1 732-562-3824, k.mccabe@ieee.org
    >
    >
    >
    > VERILOG(R) MARKS 10th ANNIVERSARY OF ITS IEEE STANDARD AND 20th ANNIVERSARY
    > OF ITS COMMERCIAL DEVELOPMENT
    >
    > IEEE Also Issues Updated Standard for Verilog Hardware Description Language
    >
    >
    > PISCATAWAY, N.J., USA, 19 Dec. 2003 The Verilog(R) language, the
    >
    >
    > predominant language for chip design and verification, celebrated two
    >
    >
    > anniversaries in late 2003. One was the 10th anniversary of the first
    >
    >
    > meeting of the IEEE 1364(TM) Working Group, which created the Verilog
    >
    >
    > standard. The other was the 20th anniversary of the commercial development
    >
    >
    > of the Verilog language
    >
    >
    > In addition, the IEEE 1364 Working Group this month released a
    >
    >
    > revision of IEEE 1364-2001, "Standard for the Verilog Hardware Description
    >
    >
    > Language (HDL)". The revision corrects certain inconsistencies and
    >
    >
    > includes important editorial changes missing in the last printing.
    >
    >
    > The IEEE Standard Verilog HDL is a common language for chip design,
    >
    >
    > simulation, verification and implementation. Chip designers use Verilog to
    >
    >
    > specify hardware in simple and concise terms with little need for redundant
    >
    >
    > entry of information. A rich ecosystem of tools exists from many suppliers
    >
    >
    > allowing users to easily and economically create chips that match the
    >
    >
    > design specified.
    >
    >
    > The Verilog HDL was developed in 1983 at Gateway Design Automation,
    >
    >
    > which was purchased by Cadence Design Systems. In 1990, Cadence formed
    >
    >
    > Open Verilog International (OVI) to promote the language as an
    >
    >
    > international open standard. In 1993, the IEEE approved OVI's request to
    >
    >
    > create a Verilog standard and accepted OVI's donation of the copyright to
    >
    >
    > the language.
    >
    >
    > The IEEE Verilog Standard Working Group first met in October 1993.
    >
    >
    > The standard it produced was approved in December 1995 and published in
    >
    >
    > 1996. A revision to the standard was published in September 2001.
    >
    >
    > Use of Verilog HDL grew rapidly as design complexity went from the 20
    >
    >
    > thousand gates per chip typical of the early 1990s to 20 million gates per
    >
    >
    > chip today. The Verilog simulator market, which totaled about $70 million
    >
    >
    > in 1995, has grown to nearly $350 million in 2002. More than 100 companies
    >
    >
    > now create and sell Verilog tools for simulation, synthesis, analysis,
    >
    >
    > power and timing estimation, functional and formal verification, and other
    >
    >
    > areas. Over 200,000 licenses for Verilog simulators are now in use.
    >
    >
    > "The creation of the Verilog standard was a major step for Verilog
    >
    >
    > users and suppliers," says Michael McNamara, who is Chair of the IEEE 1364
    >
    >
    > Working Group and Senior Vice President of Technology at Verisity. "By
    >
    >
    > making the language an IEEE standard, all vendors gained the opportunity to
    >
    >
    > develop tools that accepted this format.
    >
    >
    > "Due to the competition between tool suppliers, customers got a
    >
    >
    > better product for less money. And due to the creation of a stable format,
    >
    >
    > suppliers could confidently invest resources in developing tools for it
    >
    >
    > without fear of imminent obsolesce.
    >
    >
    > "The quantity and quality of tools supporting Verilog have improved
    >
    >
    > dramatically since 1993, so the language has remained relevant for
    >
    >
    > successive chip generations. At this time, the IEEE 1364 Working Group is
    >
    >
    > developing the next IEEE 1364 version that will address the complex needs
    >
    >
    > of today's circuit design teams. The new version will remain true to the
    >
    >
    > roots of the original language, yet leverage higher levels of abstraction
    >
    >
    > and add a range of proven packages containing powerful constructs and
    >
    >
    > utilities. We hope to complete this effort in mid 2005."
    >
    >
    >
    >
    >
    > About IEEE 1364 Working Group
    >
    >
    > To learn more about the IEEE 1364 Working Group and the next version
    >
    >
    > of the Verilog standard, visit http://www.verilog.com. The group holds a
    >
    >
    > teleconference at
    >
    >
    > 8:30 a.m. Pacific time on the first Monday of each month. Work on the
    >
    >
    > standard is done through task forces, each of which focuses on a specific
    >
    >
    > aspect of the language. Participation in the IEEE 1364 Working Group is
    >
    >
    > open to anyone is interested in the IEEE 1364 standard.
    >
    >
    >
    >
    >
    > About the IEEE Standards Association
    >
    >
    > The IEEE Standards Association, a globally recognized
    >
    >
    > standards-setting body, develops consensus standards through an open
    >
    >
    > process that brings diverse parts of an industry together. These standards
    >
    >
    > set specifications and procedures based on current scientific consensus.
    >
    >
    > The IEEE-SA has a portfolio of more than 870 completed standards and more
    >
    >
    > than 400 standards in development. Over 15,000 IEEE members worldwide
    >
    >
    > belong to IEEE-SA and voluntarily participate in standards activities. For
    >
    >
    > further information on IEEE-SA see: http://www.standards.ieee.org.
    >
    >
    >
    >
    >
    > About the IEEE
    >
    >
    > The IEEE has more than 380,000 members in approximately 150
    >
    >
    > countries. Through its members, the organization is a leading authority on
    >
    >
    > areas ranging from aerospace, computers and telecommunications to
    >
    >
    > biomedicine, electric power and consumer electronics. The IEEE produces
    >
    >
    > nearly 30 percent of the world's literature in the electrical and
    >
    >
    > electronics engineering, computing and control technology fields. This
    >
    >
    > nonprofit organization also sponsors or cosponsors more than 300 technical
    >
    >
    > conferences each year. Additional information about the IEEE can be found
    >
    >
    > at http://www.ieee.org.
    >
    >
    > # # #
    >
    >
    >
    > Verilog is a registered trademark of Cadence Designs Systems, Inc.
    >
    >
    > Karen McCabe
    > Senior Marketing Manager, IEEE Standards
    > 445 Hoes Lane, PO Box 1331
    > Piscataway NJ 08855 USA
    > PH: +1 732 562 3824
    > email: k.mccabe@ieee.org
    > http://standards.ieee.org
    >
    >

    This archive was generated by hypermail 2.1.4 : Fri Dec 19 2003 - 13:51:02 PST and
    sponsored by Boyd Technology, Inc.