Re: PSL: Attributes for Verilog and SystemVerilog

From: Michael McNamara (mac@verisity.com)
Date: Wed Mar 17 2004 - 14:56:54 PST

  • Next message: Alec Stanculescu: "Re: PSL: Attributes for Verilog and SystemVerilog"

    -- On Mar 17 2004 at 22:03, Shalom.Bresticker@motorola.com sent a message:
    > To: alec@fintronic.com, mac@verisity.com,
    > cliffc@sunburst-design.com, btf@boyd.com, vfv@eda.org
    >
    > Subject: "Re: PSL: Attributes for Verilog and SystemVerilog"
    > However, there are disadvantages as well.
    >
    > If we compare a psl block to a specify block, then first it adds
    > two new keywords. Who says that psl is the end and that there won't
    > be a need for another new block type and then another and another?

    We could do:

    foreign (* type = "psl" *)

    endforeign

    > Second, the exact grammar of specify blocks is specified in the Verilog
    > language. Will we have to do that with psl blocks as well?

    My proposal is that we would not do this.

    The foreign language could use what ever syntax it wanted. If
    however, it wanted to reference Verilog variables, it would have to
    define some hook up method (in my minde the right way is by using
    attributes. Alternatively, as with SPecify blocks, one could do this
    by using the same variable naming conventions as verilog and depending
    on the tool to parse the module to find the variables).

    module top;
     joe j1 ();
     bar bar_one ();
    endmodule

    module joe;
     reg foo;

     foreign (* type = "psl", a = foo, b = top.bar_one.cpudata *)
      assume a => b unless hell_freezes_over;
     endforeign

    endmodule
    ...

    > Third, if we look at SV Assertions as well, due to their close
    > alignment with PSL, is it logical to have completely separate
    > mechanisms for SVA and PSL when they have the same core language?

     The issue here is how do you embed PSL in Verilog.

     Great effort has gone into making SVA a proper subset of PSL, and
     even if this could have been achieved (it wasn't) there is still the
     need to embed code that uses PSL constructs that aren't in the SVA
     subset. This is the issue before us.

    > Fourth, an advantage of the pragma/attribute approach is that you write
    > them adjacent to the place where they are relevant instead of at the end
    > of the module, far away.

     There is no restriction on where specify blocks may occur, nor how
     many you can include in a module. I would presume we do the same here
     with PSL and/or foreign blocks.

     It even is the case that while '(*PSL="' and '"*)' uses up 10
     characters, 'psl' 'endpsl' uses up only 9, so the psl..endpsl
     container is arguably less intrusive to the reader than using
     attributes.

    > There are probably solutions to all of these, but it is important to
    > recognize that there are issues that have to be dealt with and not get
    > into the same complications again that there were and are with config
    > blocks, for example.

     I absolutely agree, and this is why I'd love to have representatives
     from the PSL group visit us and we talk about them live. This email
     exchange however is useful to flush out many issues ahead of time as
     well.

    > Shalom
    >
    >
    > On Wed, 17 Mar 2004, Alec Stanculescu wrote:
    >
    > > Mac,
    > >
    > > I fully support your idea of how to include PSL into Verilog and I am
    > > even more adamant about not changing the Attribute construct
    > > introduced in Verilog 2001.
    > >
    > > The advantage of the proposed method over the current one where PSL is
    > > not embedded is that it will support object oriented description (each
    > > module will have its PSL description within it) and will reduce the
    > > need for lengthy external references.
    > >
    > > Formal comments used for PSL is the poor and intelligent man's approach
    > > to the problem. It is not a long term solution, we all agree on that.
    >
    > --
    > Shalom Bresticker Shalom.Bresticker@motorola.com
    > Design & Reuse Methodology Tel: +972 9 9522268
    > Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890
    > POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478
    >
    > [x]Motorola General Business Information
    > [ ]Motorola Internal Use Only
    > [ ]Motorola Confidential Proprietary

    This archive was generated by hypermail 2.1.4 : Wed Mar 17 2004 - 14:40:43 PST and
    sponsored by Boyd Technology, Inc.