Fwd: Re: PSL: Attributes for Verilog and SystemVerilog

From: Stefen Boyd (stefen@boyd.com)
Date: Wed Mar 17 2004 - 22:25:20 PST

  • Next message: Adam Krolnik: "Re: PSL: Attributes for Verilog and SystemVerilog"

    bounced...

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    >From: VhdlCohen@aol.com
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    >Date: Wed, 17 Mar 2004 18:06:44 EST
    >Subject: Re: PSL: Attributes for Verilog and SystemVerilog
    >To: mac@verisity.com, Shalom.Bresticker@motorola.com
    >CC: alec@fintronic.com, cliffc@sunburst-design.com, btf@boyd.com, vfv@eda.org
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    >In a message dated 3/17/2004 2:59:40 PM Pacific Standard Time,
    >mac@verisity.com writes:
    >
    >'psl' 'endpsl' uses up only 9, so the psl..endpsl
    >container is arguably less intrusive to the reader than using
    >attributes.
    >
    >I like the psl endpsl block idea because users tend to put several PSL
    >statements in one block, typically before the RTL. Thus, a single
    >psl endpsl
    >looks very attractive, and by far not intrusive.
    >psl
    >... psl statements
    >... psl stateements
    >endpsl
    >-----------------------------------------------------------------------------
    >Ben Cohen Trainer, Consultant, Publisher (310) 721-4830
    >_http://www.vhdlcohen.com/_ (http://www.vhdlcohen.com/) vhdlcohen@aol.com
    >Author of following textbooks:
    >* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004 isbn
    > 0-9705394-6-0
    >* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
    >0-9705394-2-8
    >* Component Design by Example ", 2001 isbn 0-9705394-0-1
    >* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
    >* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
    >------------------------------------------------------------------------------
    >
    >-------------------------------1079564804
    >Content-Type: text/html; charset="US-ASCII"
    >Content-Transfer-Encoding: quoted-printable
    >
    ><!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
    >In a message dated 3/17/2004 2:59:40 PM Pacific Standard Time,=20
    >mac@verisity.com writes:
    ><= FONT=20 style=3D"BACKGROUND-COLOR: transparent" face=3DArial
    >color=3D#000000 size= =3D2>'psl'=20 'endpsl' uses up only 9, so the
    >psl..endpsl
    >container is arguably less=20 intrusive to the reader than using
    >attributes.
    ><= /DIV>
    >I like the psl endpsl block idea because users tend to put severa= l=20
    >PSL statements in one block, typically before the RTL. Thus, a single=20=
    >psl=20 endpsl looks very attractive, and by far not intrusive.
    >psl
    >... psl statements
    >... psl stateements
    >endpsl
    >
    >
    >---------------------------------------------------------------=
    >--------------
    >Ben=20 Cohen Trainer, Consultant, Publisher (310) 721-4830
    ><3d.htm>http://www.vhdlcohen<3d.htm>.com/=20 vhdlcohen@aol.com
    >Author of following textbooks:
    >* Using PSL/SUGA= R=20 for Formal and Dynamic Verification 2nd Edition,
    >2004 isbn=20 0-9705394-6-0
    >* Real Chip Design and Verification Using Verilog and=20 VHDL, 2002 isbn
    >0-9705394-2-8
    >* Component Design by Example "= ,=20 2001 isbn 0-9705394-0-1
    >* VHDL Coding Styles and Methodologies, 2nd=20 Edition, 1999 isbn
    >0-7923-8474-1
    >* VHDL Answers to Frequently Aske= d=20 Questions, 2nd Edition, isbn=20
    >0-7923-8115
    >-------------------------------------------------------------=
    >-----------------
    >
    >-------------------------------1079564804--

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