RE: PSL: Attributes for Verilog and SystemVerilog

From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Thu Mar 18 2004 - 18:01:22 PST

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    Hi, All -

    Erich always gives good, well reasoned comments. I enjoy engaging him in
    these discussions. I have been out of town (and out of my mind) for the
    past three weeks and barely even had time to participate in this frackus!

    At 06:42 PM 3/17/2004, Erich Marschner wrote:
    >Mac, Shalom,
    >
    >I'm glad to see that the question of how to embed PSL code into Verilog is
    >of such interest.
    >
    >I'd like to point out that there are several options for embedding PSL
    >assertions into an HDL description, and there are several languages
    >(Verilog, VHDL, SystemC, SystemVerilog) with which PSL can potentially be
    >used. The approach taken so far - structured comments - has had some
    >advantages:
    >
    > - the approach can be used in Verilog, VHDL, SystemC, etc.

    Agreed. In many respects, Verilog-2001 attributes are comments. They just
    happen to be comments that tools will parse to see if there is content that
    is important to the tool. This is why for Verilog-1364.1-2002, we require
    that the first attribute word be "synthesis" to notify tools that this
    comment was intended for synthesis tools, which may also be important to
    other tools such as formal verification tools.

    > - no changes were required in those languages (works with current versions)

    Almost true of attributes. I really think we over-defined attributes for
    Verilog-2001 and may want to change their definition for Verilog 200x. In
    my opinion, the idea behind attributes was to move pragmas out of comments
    and into pseudo-comments so that tools no longer had to parse comments.

    I think we over-structured attributes and should relax their structure in
    the IEEE 1364 standard. I would like to see PSL added to attributes without
    modification to PSL.

    In my opinion, if PSL cannot be described in attributes, then attributes
    are broken.

    Stu Sutherland noted that the VPI depends on attributes to be defined as
    they are today to extract information, but he also said that perhaps the
    VPI should just read attribute strings and allow tools to parse the
    strings. I would agree with the latter.

    > - embedded PSL is transparent to tools that are not yet PSL-aware

    Attributes would permit this.

    >...

    >Although this question is clearly of interest to those of us working on
    >PSL, I believe the issues are largely in the Verilog domain - i.e., what
    >works best within the Verilog 1364 standard. I would suggest that the
    >main constraints from the PSL side are the following:
    >
    > - Embedded PSL should be allowed to appear 'anywhere' in the design
    > (where 'anywhere' means at least before/after any statement).

    I agree, which is why I think attributes need to change to allow this.

    > - Embedded PSL should follow standard PSL syntax.

    Agreed, as noted above.

    > - Embedded PSL should be able to reference any Verilog identifiers
    > visible at
    > the place where the PSL is embedded.

    Agreed, with Adam Krolnik's friendly amendment.

    >Regards,
    >
    >Erich Marschner
    >Cadence

    There have been other notes about:
    psl begin - end psl.

    I don't like those ideas for a few reasons.

    (1) At this point, not all tools intend to support PSL. Notably, Synopsys
    has so-far announced that they will not be supporting PSL.

    (2) SystemVerilog Assertions (SVA) already adds nearly all the same
    functionality (and some additional functionality) as PSL with a
    very-PSL-like syntax. Sequences, properties, assertions, procedural
    assertions and actions blocks are all part of SVA. Action blocks were not
    added to PSL for reasons that Erich expounded on the VFV reflector (I
    believe mostly having to do with the fact that PSL was targeted to multiple
    HDLs and PSL did not want to be in the procedural language arena for all of
    the supported languages). Nevertheless, Synopsys engineers at SNUG this
    week shared interesting synthesis potential related to assertions that
    included action blocks, capabilities that I would like to see.

    Although SVA has not been adopted into IEEE-Verilog, I like the syntax
    better than PSL (where there are a few differences). I still like ## for
    cycles (Verilog # is a delay - Vera @ is a cycle delay but it looks too
    much like an edge trigger in Verilog - PSL ";" is a cycle delay but it
    looks too much like the end of a Verilog statement).

    I like the idea of SVA being Verilog-like in syntax and built into the
    language with accompanying keyword and allowing PSL to be added in the
    comment-like attributes without any modification to the final PSL syntax.

    This ought to be good for some more discussion on the respective
    reflectors! ;-)

    Regards - Cliff

    ----------------------------------------------------
    Cliff Cummings - Sunburst Design, Inc.
    14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
    Phone: 503-641-8446 / FAX: 503-641-8486
    cliffc@sunburst-design.com / www.sunburst-design.com
    Expert Verilog, SystemVerilog, Synthesis and Verification Training

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