RE: PSL: Attributes for Verilog and SystemVerilog

From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Sun Mar 21 2004 - 22:51:10 PST

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    Hi, All -

    My bad! I don't work for an company that sells EDA tools and I forgot the
    new bylaws that forbid mention of companies and product plans. I will
    refrain from mentioning companies in future discussions.

    I hope the issues I raised do not get lost in my poor presentation of same.

    Sorry, all!

    Regards - Cliff

    At 06:49 AM 3/23/2004, Michael McNamara wrote:

    >-- On Mar 18 2004 at 18:01, Clifford E. Cummings sent a message:
    > > To: btf@boyd.com, vfv@eda.org
    > > Subject: "RE: PSL: Attributes for Verilog and SystemVerilog"
    > > Hi, All -
    >...
    > > There have been other notes about: psl begin - end psl.
    > >
    > > I don't like those ideas for a few reasons.
    >...
    > > This ought to be good for some more discussion on the respective
    > > reflectors! ;-)
    >...
    > >
    > > (1) At this point, not all tools intend to support PSL. Notably, Synopsys
    > > has so-far announced that they will not be supporting PSL.
    >
    >Cliff - I in an odd way want to thank you. You have made a picture
    >perfect forbidden statement here, introducing a consideration that has
    >no place on IEEE SA reflectors, as well as no place at any meeting or
    >discussion forum that is supported by a 503(c) corporation operating
    >in and under the laws of the United States, such as the IEEE.
    >
    >You have introduced a business related consideration into a standards
    >process. I must remind you (and everyone else on the IEEE reflector)
    >that we must be completely blind to business considerations when we
    >are operating as members of a standards group. We check such
    >considerations at the door, and pick them up again when we leave.
    >
    >The fact that a company has announced support, or promised lack of
    >support for a proposed (or even something that may be proposed as an )
    >element of the standard is something that we can not introduce or
    >discuss in IEEE standards mailing lists, IEEE standards conference
    >calls or any other IEEE standards forum. You are welcome to think
    >them in your mind; but when you talk, and when you vote, you are
    >required to operate for the general good of the public.
    >
    > > (2) SystemVerilog Assertions (SVA) already adds nearly all the same
    > > functionality (and some additional functionality) as PSL with a
    > > very-PSL-like syntax. Sequences, properties, assertions, procedural
    > > assertions and actions blocks are all part of SVA. Action blocks
    > > were not added to PSL for reasons that Erich expounded on the VFV
    > > reflector (I believe mostly having to do with the fact that PSL was
    > > targeted to multiple HDLs and PSL did not want to be in the
    > > procedural language arena for all of the supported
    > > languages). Nevertheless, Synopsys engineers at SNUG this week
    > > shared interesting synthesis potential related to assertions that
    > > included action blocks, capabilities that I would like to see.
    >
    >Again, this strays into a forbidden area. Discussion on the plans of
    >various companies to do, or not do something based on syntax gets into
    >anti-trust areas which we must avoid.
    >
    >You could say that "I recently spoke with synthesis experts who shared
    >interesting ideas related to assertions that include action blocks,
    >ideas that I would like to see added to the language." and thereby
    >convey the point that knowledgeable people with whom you are
    >acquainted see ways to use particular syntax to further the general
    >good.
    >
    >However, the way you indeed phrased this also includes an implied
    >business threat which presumably you did not intend: that employees
    >from a particular company favored a syntax because it gives them some
    >sort of advantage (perhaps only in obtaining your business), and that
    >we on the committee should take action (perhaps to facilitate or foil,
    >it is hard to tell) based on this.
    >
    >Again, having worked with you for years, I do not believe this was
    >your intent. However, this is an open process, and people you do not
    >know you will read this and could infer that you were attempting to
    >steer the standard in a way that might favor one company over another;
    >something the IEEE will not condone. (The IEEE-DASC brought your
    >email to my attention, by the way).
    >
    >Again, all should refer to
    >http://standards.ieee.org/resources/StdsLaw_Brochure.pdf
    >for more detail on these pitfalls.
    >
    >I will spend some time at the beginning of the next IEEE Verilog
    >meeting going over this again in order to remove any doubt.
    >
    > Michael McNamara, Chairman, IEEE 1364 Working Group <mac@verilog.com>
    > W 650-934-6888 F 650-934-6893 M 408-930-6875

    ----------------------------------------------------
    Cliff Cummings - Sunburst Design, Inc.
    14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
    Phone: 503-641-8446 / FAX: 503-641-8486
    cliffc@sunburst-design.com / www.sunburst-design.com
    Expert Verilog, SystemVerilog, Synthesis and Verification Training

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