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A resend of the VSG ballot
> Hi Kurt,
>
> I'm on the 1364 reflector, but I did not receive this ballot for some
> reason. Perhaps it would be safer if you were to send a message to
> each eligible voter individually, at least to see if they got the
> ballot?
I am hoping this gets to everyone.
This is the P1364 VSG electronic ballot.
------------------------------------- this wide please
-------------------------------------------------
>From our P1364 procedures:
The Returning Officer shall conduct the election by letter or
electronic ballot.
Voting shall be by "approval", whereby each balloter may cast an
approval
vote for each of any number of nominees for an office. The
nominee with the
greatest number of approval votes shall win the election.
Write-in candidates
are permitted as specified in IEEE Bylaws. In the event of a
tie, the Returning
Officer shall decide between the tied candidates by picking a
candidate's
name from a hat.
I have my genuine "ten-gallon" Stetson here just in case!
>From the VSG meeting:
Meeting called to order 8:30 May 17th, 2004
Attendance:
Today DASC member (D yes, - no)
| |
v v
---+--------------------------------------------------------------
Aaa|aaaaaaaaaaaaaaaaaaaa D Michael McNamara <verisity>
Aaa|aaaaaaaaaaaaaaaaa-aa D Steven Sharp <cadence>
Aaa|aaaaaaaaaaaaaaaaa-aa D Karen Pieper <synopsys>
Aaa|aaaaaaaaa-aaaaaaaaa- D Shalom Bresticker <motorola>
Aaa|aaaaaaaaa-aaaaaaa-a- D Charles Dawson <cadence>
Aaa|aaaaaaaaa D Francoise Martinolle <cadence>
Aaa|aaaa-aaa-aaaa------- D Kurt Baty <wfsdb>
Aaa|aa-a-aa D Keith Gover
Aaa|aa--aaaa------a--aa- D Tom Fitzpatrick <synopsys>
Aaa|a-aaaaaaaaaaaa----aa D Brad Pierce <synopsys>
Aaa|a-a D Ronald Goodstein
Aaa|a--aaaaa D Alec Stanclulesco <fintronic>
Aaa|-aaaaa-aa-aaaaaaaaaa D James A. Markevitch <Evegreen Technology>
Aaa|--aaa-----aa-a---aaa D Clifford E. Cummings <sunburst-design>
Aa-|aa-aa-aaa D Dennis Brophy <model>
Aa-|a-aa----a D Steven Dovich <cadence>
Aa-|-aaaaa-aa----------- D Drew Lynch <verisity>
A-a|aaaaaa-a---aaaaa-aa- D Stuart Sutherland <sutherland-hdl>
A-a|-aaaa D Richard Ho
---+--------------------------------------------------------------
-a-|aa-aaaa D Ennis Hawk <Jeda>
A--|aaaaa--aa-a-aaaaaaa- D Stefen Boyd <boyd>
---|a------------------ - Yogesh Goel <axis, now verisity>
---|-a---a--a D Karen Bartleson <synopsys>
---|--aaaa-----a------- D Mehdi Mohtashemi <synopsys>
---|--a---a--a--------- - Krishna Garlapati <synplicity>
---|----a--aa-aaaaaaaaaa D Anders Nordstrom <cadence>
---|----a D Atsushi <Jeda>
---|-----aa D Don Mills <lcdm-eng.com>
---|------aaa D Jay Lawrence <cadence>
---|------a-aaaaaaaaa-aa D Gordon Vreugdenhil
---|------a D David Smith <synopsys>
---|------a D Chong Guan Tan <verisity>
---|----------aaaaaaaaaa - Dennis Marsa <xilinx>
---|------------------aa - Erich Marchner <cadence>
---|-------------------a D Peter Flake <synopsys>
>From this Attendance List I get the following list of eligible voters (I
am not eligible):
Michael McNamara
Steven Sharp
Karen Pieper
Shalom Bresticker
Charles Dawson
Francoise Martinolle
Keith Gover
Tom Fitzpatrick
Brad Pierce
Ronald Goodstein
Alec Stanclulesco
James A. Markevitch
Clifford E. Cummings
Dennis Brophy
Steven Dovich
Drew Lynch
Stuart Sutherland
Richard Ho
The election shall end either when I receive ballots from all of the
eligible voters
or at 5pm US Pacific time, Thursday May 27, 2004. To that end I would
request
that all eligible voters return this ballot to me even if they do not
wish to make any
"approval" votes. When I received your ballot I will email you
confirmation.
------------------------------------- this wide please
-------------------------------------------------
The Candidates for the Office of Chairman of P1364 VSG are:
[ ] Michael McNamara
I seek your vote to re-elect me as chair of the IEEE
1364
Working Group so that we can deliver upon our Scope and
Purpose, as defined in the PAR we were granted on March
of 2003:
Verilog is a Hardware Description Language which was
standardized as IEEE-1364-1995, and revised as
1364-2001.
It is currently used by integrated circuit designers
to specify their designs at the switch, gate, RTL and
system levels. The proposed project will revise
Verilog
1364 to clarify features ambiguously described in the
1364-1995 and 1364-2001 revisions, as well as to
extend
the language by adding new constructs which improve
the
utility of the language both at the detailed physical
level and at high levels of abstraction to meet
industry
needs for improved design and verification technology.
I will strive to knit together a consensus of all of the
implementors and the users so that we can have an build
open marketplace where the language is well defined and
the process is open to contributions from all.
Michael McNamara
[ ] Karen Pieper
I have been an active contributor to the IEEE-1364 VSG
for the last 10 years, most recently serving as the
chair of the Errata Task Force. Under my leadership,
we were able to resolve a large number of issues
confronting both tool vendors and users. With my joint
experience in simulation and synthesis, I have been
able to bring a unique perspective to the analysis of
proposed enhancements.
I have also served as the Co-Chair of the SystemVerilog
Basic/Design Committee within Accellera. In this role,
I have been able to work with a team whose members hold
many different perspectives and to build a standard that
reflects multiple requirements and uses. As a result,
SystemVerilog is 100% aligned with and built upon
Verilog-2001.Going forward, it is critical that Verilog
and SystemVerilog continue to deliver one definition of
Verilog to the Verilog community. If elected, I will use
all of the leadership skills I have learned working
within the standards community to deliver one definition
and to better Verilog for both users and vendors.
Respectfully submitted,
Karen Pieper
[ ] Write-in _______________________________________
------------------------------------- this wide please
-------------------------------------------------
The Candidates for the Office of Vice-Chairman of P1364 VSG are:
[ ] Tom Fitzpatrick
I have been an active member of the 1364 VSG since 1995,
and have always worked to make Verilog a more valuable
standard for users. Although my experience on the VSG
has
always been as a member of a vendor company, my role in
each of those companies is to represent the user
community
(having been a hardware and verification engineer for
nearly 10 years prior to moving over to EDA) and
advocate
for tool features, use-models, and language enhancements
that would improve the ability of users to get their
jobs
done. As such, I believe I hold a unique perspective to
facilitate discussions and negotiations between the
often
non-aligned goals of users and vendors in advancing such
a standard.
In addition to the VSG, I have also been an active
participant in the Accellera SystemVerilog committees as
well as a member of the Superlog language design team at
Co-Design Automation. I make no secret of my support for
SystemVerilog as a valuable standard providing a common
language for both design and verification, and I believe
that my past experience on standards committees,
including
the VSG, affords me the ability to work with all members
of the VSG and Accellera to enable us to reach consensus
on a solution that advances Verilog while not ignoring
users' and vendors' investment in SystemVerilog. It is
my
sincere belief that this path will enable us to create
the
best standard, that is both usable and implementable, as
the industry continues to make giant strides forward. I
thank you for the opportunity to serve in this effort.
Respectfully submitted,
Tom Fitzpatrick
[ ] Alec Stanculesc
After receiving a PhD in EE from Stanford University
in 1986, with a thesis on the simulation of multi-
processing architectures, I co-authored four books on
HDLs published by Kluwer Academics, and several articles
published in major journals and proceedings of major
conferences on the topics of HDLs. I also managed the
development of a VHDL simulator at Vantage Analysis
Systems (as manager of simulation), and participated
from 1985 in the standardization of VHDL, and from
1992 in the standardization of Verilog (first within
OVI and then as vice-Chair of the IEEE 1364 WG, for
both 1995 and 2001 versions of the language). I attended
most face to face meetings for the standardization of
System Verilog and followed it's development closely.
As president of Fintronic USA, I managed the development
of a Verilog simulator (FinSim) which sold it's first
copy on Linux in 1993 and has sold to date over 4000
licenses to over 400 different entities and which
contributed many new concepts to the state of the art
of Verilog simulation.
Currently, I am a member of ANSI and a representative
of the US to the TC 93 Committee of the IEC, as well
as convener of the WG1 of IEC TC93, dealing with
interoperability of hardware design tools. Over the
years I was a strong supporter of making Verilog an
IEC standard and I am very happy to report that Verilog
has been very recently voted a dual-logo IEC-IEEE
standard. I believe that a strong co-operation between
IEEE and IEC is important for the world-wide adoption
of Standards in HDLs and of Verilog in particular.
As vice-chair of IEEE 1364 I will continue to represent
the interests of IEEE 1364 within IEC and at the same
time help the evolution of Verilog to the best interest
of it's users and tool suppliers by contributing to the
integration of System Verilog into Verilog 2005 in
an objective way.
Regards,
Alec Stanculescu
[ ] Write-in _______________________________________
------------------------------------- this wide please
-------------------------------------------------
The Candidate for the Office of Secretary of P1364 VSG is:
[ ] Keith Gover
I originally became involved with the IEEE through the
student chapter at my university where I held a number
of positions. For the past 7 years I have worked both
as a hardware designer using Verilog and in EDA
supporting
designers doing Verilog simulation. Although I have
always followed the activities of the standards
organizations I have not been directly involved until
recently. Over the past year I have been slowly trying
to become more involved with IEEE through participation
in the 1364 working group. I am very excited about all
that is happening with the Verilog language today and
very much look forward to contributing everything I can
to the evolution of the language. As the Secretary for
the 1364 working group I will record and maintain the
minutes of all business meetings as well as any other
duties necessary for the successful operation of the
group.
Thanks,
Keith Gover
[ ] Write-in _______________________________________
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