Why do bit-lengths have to be computable at compilation time?

From: Shalom.Bresticker@freescale.com
Date: Sun May 30 2004 - 02:44:49 PDT

  • Next message: Gordon Vreugdenhil: "Re: Why do bit-lengths have to be computable at compilation time?"

    This question comes up repeatedly, most recently in a discussion on
    comp.lang.verilog with respect to parameterized functions.

    Paul Graham wrote in http://www.eda.org/vlog-pp/hm/0572.html:

    "NC-VHDL handles constructs whose length is uncomputable at compilation time
    (variable-length slices and aggregates). Since NC-VHDL is also a native
    code compiled simulator, there must be another reason. Probably the same
    reason that verilog disallows all other variable-length constructs -- they
    don't correspond to real hardware."

    So can someone give a convincing explanation why Verilog does require
    pre-computable lengths?

    Maybe we've gotten that explanation in the past and I am just senile,
    but I don't remember, so please humor me.

    And then the next question is, even though that has been the situation
    in the past, does it have to be that way in the future? 

    -- 
Shalom Bresticker                         Shalom.Bresticker @freescale.com
Design & Reuse Methodology                            Tel: +972 9  9522268
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