From: Brad Pierce (Brad.Pierce@synopsys.com)
Date: Thu Jun 24 2004 - 14:12:16 PDT
Note that 'var' is a reserved, but unused, keyword in
SystemVerilog 3.1A. According to the note below Table B-1,
it is "reserved for future extensions".
> might require the addition of another keyword (such as "var") to allow
> unambiguous declaration of variables in some situations.
-- Brad
This archive was generated by hypermail 2.1.4
: Thu Jun 24 2004 - 14:12:27 PDT
and
sponsored by Boyd Technology, Inc.