Re: Requesting datatypes feedback

From: Daryl Stewart (daryl.stewart@tenison.com)
Date: Tue Jun 29 2004 - 05:43:29 PDT

  • Next message: Alec Stanculescu: "Re: Requesting datatypes feedback"

    Steven Sharp wrote:

    >Here is an attempt to provide the examples that Stu asked for.
    >
    >

    I don't see how either introduces backwards compatibility issues with
    either V2K1 or SystemVerilog, although it would of course introduce
    forwards compatibility issues (i.e. V2K5 would correctly interpret V2K1
    and SV decls, but V2K1 and SV might refuse some of the proposed forms)
    as do most enhancements.
    Can someone illustrate a SV declaration which either of the two
    solutions interprets substantially differently?

    I don't see why var is needed.
    What declaration would be ambiguous and how?

    IMHO the first option is preferable (reg as object kind meaning variable)
       No new keyword is needed (apparently ;)
       The concept of reg as a variable kind from V2K is preserved.

    For V2K, the spirit of reg seemed to be as an object kind. It
    distinguished the use, not the type. It just so happened that V2K didn't
    have 2-state datatypes, so it was always 4-state. I would also suggest
    that even SV denotes variable kind with reg:

    From Minutes of BTF meeting on June 28, 2004:

    >Steve Sharp said that SystemVerilog uses reg as a type
    >declaration. However, as objects of complex data type can be also
    >formal ports there may be problems.
    >
    >Kurt: reg should become type.
    >Stu: if reg becomes type then PLI will be affected.
    >
    The use of reg in SV (as I understand it, which is possibly not much ;)
    denotes more than just the type, partly due to the lack of
    orthogonality. Unless my BNF (from SystemVerilog_3.1a) is out of date,
    you cannot say "wire reg" or "wire logic". In fact, I can't see how you
    can say "wire data_type" at all.

    net_declaration ::=
    net_type_or_trireg [ drive_strength | charge_strength ] [ vectored | scalared ]
    [ signing ] {packed_dimension} [delay3] list_of_net_decl_assignments ;

    net_type_or_trireg ::= net_type | trireg

    net_type ::= supply0 | supply1 | tri | triand | trior |
    tri0 | tri1 | wire | wand | wor

    and also

    variable_declaration ::=
    data_type list_of_variable_decl_assignments

    So reg appears to denote not only the type of the declared object (4
    state, not 2), but also its kind (if you say reg, it *must* be a variable)
    Of course, SV variables can also be continuously assigned (no more than
    once).

    Furthermore, when a "complex datatype port" is declared, it is a
    variable, not a net, which is used. This works because the variable is
    allowed to model the port by using its allowance of one continuous
    assignment. See section 5.6 of 3.1a for clarification of the rules
    proscribing further continuous assignments to variables connected to ports.

    So neither V2K nor SV have Soln2's ugly:
    wire reg [7:0] wr; // Its 4 state but is it a variable or a net? (net)

    OTOH an SV user may find the following from Soln1 a bit confusing:
    reg bit [7:0] r; // its a variable, but is it 2 or 4 state? (2)
    reg logic [7:0] r; // redundant sounding

    I think it would be nice to preserve the data kind spirit of reg which I
    believe is used in
    both V2K and SV.

    If you really want a keyword to emphasise the distiction of variable vs.
    net, perhaps var could be a kind equivalent to reg kind.

    cheers
    Daryl 

    -- 
Tenison Technology
System Emulation in Software

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