From: Alec Stanculescu (alec@fintronic.com)
Date: Fri Jul 02 2004 - 10:35:50 PDT
Daryl,
I do not agree that we will have to quiet down. On the
contrary. Actually, all we need in order to have a pleasant and
constructive exchange of ideas is a reflector. All we need in order
for our ideas to have an impact on the actual standardization process
for Verilog is to participate in an organization that is part of the
standardization process.
The important facts are:
1. Verilog is the most widely used hardware description language
today.
2. An extremely large number of useful extensions are relatively
clearly specified, but not yet implemented.
3. Most EDA companies have expressed interest in implementing at least
some if not all the extension features that are currently described in
various places.
4. Most EDA companies have tight budgets and would not want to embark
on a wild goose chase and implement features that are not perfectly
specified and agreed upon by a majority of EDA vendors and users.
5. Due to active and efficient lobbying by interested parties, the IEEE
has chosen to re-organize how the future standardization of Verilog
shall proceed.
6. There are several forums where interested parties can participate
in this process. Some of us will participate in several such forums.
7. Many EDA companies, as well as companies using EDA tools will join
most of these forums, so I am sure that we will have many more chances
to communicate.
The only true danger resulting from the current changes is that the majority of
the DASC-SC members have had little or no experience with Verilog and
may not appreciate appropriately all the work in progress. As a result,
there is some risk that a lot of work in progress may be lost. I am
sure that efforts will be made to prevent this from happening.
Best regards,
Alec
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